Merge "fix(qti): harden mem_assign parameter handling" into integration

Merge "fix(xilinx): use bool in control expressions" into integration

Merge changes from topic "amd_feat_dyn_core_clust" into integration

* changes:
feat(versal2): update plat psci based on dynamic core and cluster
feat(versal2): add dynamic fetching of core and c

Merge changes from topic "amd_feat_dyn_core_clust" into integration

* changes:
feat(versal2): update plat psci based on dynamic core and cluster
feat(versal2): add dynamic fetching of core and cluster
refactor(xilinx): promote map/unmap helpers to public scope
feat(versal2): use runtime core/cluster variables for dyn topology

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fix(qti): harden mem_assign parameter handling

Copy mem_assign input buffers to secure local storage before validating
their contents.

The previous code validated entries by walking non-secure buff

fix(qti): harden mem_assign parameter handling

Copy mem_assign input buffers to secure local storage before validating
their contents.

The previous code validated entries by walking non-secure buffers
directly after mapping them. This keeps validation dependent on
non-secure memory and makes the arithmetic around the mapped span more
fragile.

Rework the flow to:
- retrieve indirect arguments through a helper
- map the non-secure parameter span once using checked arithmetic
- verify buffer lengths before copying
- copy mem/source/destination arrays to local buffers
- validate parameters from the secure copies
- use add_overflow() for range calculations
- clear the dynamic mapping state through the helper-based flow

This reduces exposure to malformed non-secure input and avoids address
wrap issues while keeping the SMC interface unchanged.

Change-Id: Ie9e5480891a82ba98919c8c7dbdd27819e246185
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

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Merge "fix(nxp): move includes to where they are needed" into integration

Merge "feat(corstone-1000): make mutlicore support platform generic" into integration

Merge changes from topic "qti_lemans_evk" into integration

* changes:
docs(qti): add lemans_evk platform documentation
fix(qti): don't panic() without QTISECLIB
feat(lemans): add support for l

Merge changes from topic "qti_lemans_evk" into integration

* changes:
docs(qti): add lemans_evk platform documentation
fix(qti): don't panic() without QTISECLIB
feat(lemans): add support for lemans EVK platform
feat(qti): add support for Lemans SoC

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Merge changes from topic "xlnx_fix_misra_versal2" into integration

* changes:
fix(versal2): add prototype for external linkage
fix(versal2): resolve type mismatch

feat(versal2): update plat psci based on dynamic core and cluster

Update the psci logic under TFA_NO_PM which checks for core and
cluster counts based on the dynamic core and cluster information
ret

feat(versal2): update plat psci based on dynamic core and cluster

Update the psci logic under TFA_NO_PM which checks for core and
cluster counts based on the dynamic core and cluster information
retrieved from the DT blob.

Change-Id: If32f4a114099eca5d8961ff89e481257ebca49c1
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(versal2): add dynamic fetching of core and cluster

Add dynamic fetching of core and cluster information from device tree
blob and on failure fallback to default configurations of Versal Gen 2.

feat(versal2): add dynamic fetching of core and cluster

Add dynamic fetching of core and cluster information from device tree
blob and on failure fallback to default configurations of Versal Gen 2.

Change-Id: Ide03f8a412f7155c0c85627be4fd1e0064863fc9
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(xilinx): correct node idx for Versal Gen 2

Several device node indices are incorrectly placed in the common
section of the enum but are only used in Versal Gen 2:
- XPM_NODEIDX_DEV_I2C_2 through

fix(xilinx): correct node idx for Versal Gen 2

Several device node indices are incorrectly placed in the common
section of the enum but are only used in Versal Gen 2:
- XPM_NODEIDX_DEV_I2C_2 through XPM_NODEIDX_DEV_I2C_7 (0x117-0x11C)
- XPM_NODEIDX_DEV_CAN_FD_2, XPM_NODEIDX_DEV_CAN_FD_3 (0x11D-0x11E)
- XPM_NODEIDX_DEV_TTC_4 through XPM_NODEIDX_DEV_TTC_7 (0x11F-0x122)
- XPM_NODEIDX_DEV_MMI_GEM (0x13A)

This causes incorrect XPM_NODEIDX_DEV_MAX values:
- Versal: is 0x13B, should be 0x54
- Versal Gen 2: is 0xD8 (USB_1 came after MMI_GEM in source order),
should be 0x13B to include MMI_GEM

The incorrect MAX on Versal Gen 2 causes the bounds check in
pm_client_set_wakeup_sources() to silently reject MMI_GEM
(0x13A).

Move all Versal Gen 2-specific device indices inside the
XPM_NODEIDX_DEV_MAX:
- Versal: XPM_NODEIDX_DEV_MAX = 0x54
- Versal Net: XPM_NODEIDX_DEV_MAX = 0xDF (unchanged)
- Versal Gen 2: XPM_NODEIDX_DEV_MAX = 0x13B

Change-Id: I6979758b1295782a9743301d0ad7f7cda75d1b36
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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refactor(xilinx): promote map/unmap helpers to public scope

Remove the static qualifier from add_mmap_dynamic_region() and
remove_mmap_dynamic_region() in plat_fdt.c, and add their
declarations to p

refactor(xilinx): promote map/unmap helpers to public scope

Remove the static qualifier from add_mmap_dynamic_region() and
remove_mmap_dynamic_region() in plat_fdt.c, and add their
declarations to plat_fdt.h so they can be reused across Xilinx
platform code.

When XILINX_OF_BOARD_DTB_ADDR is not defined, static inline no-op
stubs are provided to allow unconditional calls without link errors.

Change-Id: I795dbcb2b13b4e5d5fe900edabaa703d6aade0be
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(versal2): use runtime core/cluster variables for dyn topology

Replace static CORE/CLUSTER macros with variables exposed from
platform topology. These variables are updated at runtime
thereby en

feat(versal2): use runtime core/cluster variables for dyn topology

Replace static CORE/CLUSTER macros with variables exposed from
platform topology. These variables are updated at runtime
thereby enabling dynamic topology configuration.

Change-Id: Ia98e32c78c48f5e24ec152409e663f173feaccc0
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(marvell): provide a default compile target

The DDR drivers require the `CROSS_COMPILE` prefix to be set. Platform
builds break if a user builds for Marvell without explicitly providing
this. Thi

fix(marvell): provide a default compile target

The DDR drivers require the `CROSS_COMPILE` prefix to be set. Platform
builds break if a user builds for Marvell without explicitly providing
this. This is hidden in CI because we always set the target. Provide a
default as a workaround.

Change-Id: Id93d71876a81e442e6612eae2b0e7cb12e0fd55a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(a8k): declare amb_memory_map as an array

The DDR files used in CI were recently updated. They introduce a
requriement for GCC 14 and new flags into CFLAGS, including
`-Wsizeof-pointer-div`. This

fix(a8k): declare amb_memory_map as an array

The DDR files used in CI were recently updated. They introduce a
requriement for GCC 14 and new flags into CFLAGS, including
`-Wsizeof-pointer-div`. This results in the following compiler warning
when building for this platform:

```
plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c: In
function 'marvell_get_amb_memory_map': include/lib/utils_def.h:15:20:
error: division 'sizeof (struct addr_map_win *) / sizeof (struct
addr_map_win)' does not compute the number of array elements
[-Werror=sizeof-pointer-div] 15 | (sizeof(a) / sizeof((a)[0])) | ^
plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c:30:25:
note: in expansion of macro 'ARRAY_SIZE'
```

The warning occurs because ARRAY_SIZE() was used on a pointer
(amb_memory_map) instead of an actual array. In that case the expression
becomes sizeof(pointer) / sizeof(element), which does not represent the
number of elements and therefore triggers the compiler warning
-Wsizeof-pointer-div (treated as an error due to -Werror). Fix the
declaration of amb_memory_map to pacify the compiler.

Change-Id: I5608be6401bfbc1291ded85a8fbce8abe169dbe2
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(versal2): add prototype for external linkage

MISRA violation C2012-8.4:
A compatible declaration shall be visible when an object or function
with
external linkage is defined.
Added visible proto

fix(versal2): add prototype for external linkage

MISRA violation C2012-8.4:
A compatible declaration shall be visible when an object or function
with
external linkage is defined.
Added visible prototype to fix this violation.

Change-Id: Ia4b2b8077944b90c36d848e83faadbf6d2f8a0e9
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>

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fix(versal2): resolve type mismatch

This corrects MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential

fix(versal2): resolve type mismatch

This corrects MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Adjust macro definition to avoid implicit type conversion.

This corrects MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type category.
Make operands of the same essential type category.

Change-Id: I66c18422b701515947c32b0aabfc3aec4bad3dff
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>

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Merge "fix(rza): give more time to J-Link debugger" into integration

Merge "refactor(nxp): add NXP_TBBR_USE_X509 switch for TBBR flow selection" into integration

fix(rza): give more time to J-Link debugger

From J-Link v9.22, the reset sequence for RZ/A3M has been fixed to avoid
corrupting the x0 and x1 registers. However, it now takes slightly
longer to halt

fix(rza): give more time to J-Link debugger

From J-Link v9.22, the reset sequence for RZ/A3M has been fixed to avoid
corrupting the x0 and x1 registers. However, it now takes slightly
longer to halt the core, so the delay must be increased. Otherwise,
flashing may fail on subsequent attempts.

Change-Id: Ifd2a85393c1eb43408680196c792f432cf02124e
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

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feat(corstone-1000): make mutlicore support platform generic

To improve portability, testing coverage, and future platform
enablement.

- Replace FVP-only multicore checks with platform-generic chec

feat(corstone-1000): make mutlicore support platform generic

To improve portability, testing coverage, and future platform
enablement.

- Replace FVP-only multicore checks with platform-generic checks.

Change-Id: Ib52bbd8ce1850bbc7d5f72e6f29a208c3ba534d3
Signed-off-by: Alex Chapman <alex.chapman@arm.com>

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Merge "fix(qti): restrict EUD register r/w to debug builds only" into integration

Merge "fix(versal2): buffer overflow due to missing bounds check" into integration

fix(rza): staticize handle_debug_mode()

The handle_debug_mode() is called from one place only, the
bl2_early_platform_setup2() which is located in the same file.
Mark handle_debug_mode() static.

Si

fix(rza): staticize handle_debug_mode()

The handle_debug_mode() is called from one place only, the
bl2_early_platform_setup2() which is located in the same file.
Mark handle_debug_mode() static.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I47e50d363e022c4252ae3ef892ba7bbd820b6595

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refactor(nxp): add NXP_TBBR_USE_X509 switch for TBBR flow selection

Introduce NXP_TBBR_USE_X509 (default 0) to select X.509/mbedTLS
versus CSF header flows, and update fuse_fip and ddr_fip gating
to

refactor(nxp): add NXP_TBBR_USE_X509 switch for TBBR flow selection

Introduce NXP_TBBR_USE_X509 (default 0) to select X.509/mbedTLS
versus CSF header flows, and update fuse_fip and ddr_fip gating
to use this flag instead of MBEDTLS_DIR.

Change-Id: Ifabf6bbb4a05f57b060e9af3c9ae6b29b8864280
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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