refactor(rpi3): use crypto-agile measured boot

Adopt the crypto-agile measured boot API for RPi3. Replace the previous
single-algorithm hash configuration with dynamic algorithm selection.
Factor co

refactor(rpi3): use crypto-agile measured boot

Adopt the crypto-agile measured boot API for RPi3. Replace the previous
single-algorithm hash configuration with dynamic algorithm selection.
Factor common measurement logic into a shared helper, update BL1/BL2
integration, and ensure event log header generation and TPM extension
use the new multi-algorithm model.

Change-Id: Id700710ad2c893fc13614c81c01b8812e8edff7d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(fvp): use crypto-agile measured boot

Update the FVP measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection

refactor(fvp): use crypto-agile measured boot

Update the FVP measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection. Align image measurement and event log header generation with
the new hashing model and update platform glue code accordingly.

Change-Id: I4128a0c66a56df6c473c47a577d86cd38bf057f6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(tpm): changes to support TPM lib

The build system sets TPM_INTERFACE to FIFO_SPI, but this cannot be
tested by the C preprocessor. So, create new build define
TPM_INTERFACE_FIFO_SPI. Correct th

feat(tpm): changes to support TPM lib

The build system sets TPM_INTERFACE to FIFO_SPI, but this cannot be
tested by the C preprocessor. So, create new build define
TPM_INTERFACE_FIFO_SPI. Correct the #if statements to use it.

Make spi_init() in rpi3_spi.c static.
Pass timer functions as ops structure to TPM.
Remove implicit interface between TPM library and main firmware by
introducing explicit interface to allow firmware to pass structure
of function pointers to setup a timer and check whether it has elapsed.

Update build system for new TPM lib location.
Change #include statements in TPM source and header files to allow
for new directory structure.

Change-Id: Ie16b2e402b963161d7d4f35a187b9bd2765a1faa
Signed-off-by: Matthew Ellis <Matthew.Ellis@arm.com>

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Merge "feat(neoverse-rd): set the correct Arm version for rdn2" into integration

Merge "feat(fvp): load SP_PKGs with TRANSFER_LIST" into integration

Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): u

Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): update feature names and comments
fix(cpufeat): simplify AArch32 feature disablement

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Merge "fix(intel): remove invalid SDM SMMU Stream ID register from bypass list" into integration

Merge "fix(intel): prevent invalid register rejection on non-A5F4 devices" into integration

style(qemu-sbsa): wrap declaration in braces for clang

Clang errors if a label is followed directly by a declaration.
The variable `struct platform_cpu_topology topology` must be
inside a block to a

style(qemu-sbsa): wrap declaration in braces for clang

Clang errors if a label is followed directly by a declaration.
The variable `struct platform_cpu_topology topology` must be
inside a block to avoid the C23-extension diagnostic:

```
plat/qemu/qemu_sbsa/sbsa_sip_svc.c:86:3:
error: label followed by a declaration is a C23 extension
[-Werror,-Wc23-extensions]
86 | struct platform_cpu_topology topology;
| ^
```

Change-Id: I005f3eb054f8f33128403c79659ae10989c78d63
Signed-off-by: Vineel Kovvuri[MSFT] <vineelko@microsoft.com>

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Merge "feat(imx8m): keep console at runtime when building TF-A/bl31 with DEBUG" into integration

Merge changes from topic "image_decryption" into integration

* changes:
feat(fvp): extend image decryption support for FVP
fix(io): add NULL check for spec io_open FIP

Merge "fix(tc): correct register write in rng trap handler" into integration

fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build

Since commit 6edbd2d6a8ae ("fix(cpufeat): require FEAT_AMUv1p1 to
enable the auxiliary counters") the ENABLE_AMU_AUXILIARY_COUN

fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build

Since commit 6edbd2d6a8ae ("fix(cpufeat): require FEAT_AMUv1p1 to
enable the auxiliary counters") the ENABLE_AMU_AUXILIARY_COUNTERS
requires ENABLE_FEAT_AMUv1p1 to be enabled as well. Enable missing
ENABLE_FEAT_AMUv1p1 to fix the build, which was broken because the
R-Car Gen5 and FEAT_AMUv1p1 commits landed in reverse order.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I834aff7798d7a5e10014fbd9f1ac8a97908b9aab

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Merge "feat(rcar): add initial BL31 support for Renesas R-Car X5H" into integration

Merge "fix(intel): allow kernel access to TSN TBU stream control registers" into integration

Merge "fix: remove circular dependency on ENABLE_FEAT_RAS" into integration

Merge changes from topic "tc-lsc-25-cpu-libs" into integration

* changes:
feat(cpus): add support for LSC25 E-core CPU
feat(cpus): add support for LSC25 P-core CPU

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).

This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b

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feat(arm): allow custom BL2 mem params

Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this overri

feat(arm): allow custom BL2 mem params

Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this override is enabled,
the common arm_bl2_mem_params_desc.c implementation is
excluded from BL2_SOURCES. The platform must then append
its own bl2_mem_params_desc.c file to BL2_SOURCES.

Change-Id: I8e3e0ce6e9c2c55ec3feb18a45890f1716fe690b
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): enable measured boot

Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.

Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f

feat(rdaspen): enable measured boot

Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.

Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f91
Signed-off-by: Maximilian Berndt <maximilian.berndt@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- P

feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- Platform definitions and memory map for R-Car X5H
(Cortex-A720AE, 8 clusters x 4 cores)
- Platform-specific PSCI power management and topology
- SCMI-based power domain and system power management
- GICv4/Fainlight-AE interrupt controller initialization and support
- Trusted SRAM, shared memory, and crash log region setup
- SCIF console support
- Stack protector implementation for enhanced security
- Platform-specific linker script and build integration
- Various helper and initialization routines for MMU, GIC, and SCMI
- Platform-specific mailbox and boot flow handling
- Basic suspend implementation via SCP-FW
- AMU counters, SVE, PAUTH accessible to EL1

Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I04be48a55a618fe952b28283d2f85f48f7761c9a

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Merge "fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters" into integration

feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I1

feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I15556fde3740056b1eb81138d19635b507064abf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(

Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(tspd): don't forward declare tsp_vectors_t
fix(cpufeat): drop feature_panic() as unused

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fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without en

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without enabling
FEAT_AMUv1p1. As a result, the AMU_RESTRICT_COUNTERS may not take
effect, making this configuration potentially insecure.

Fix this by adding a constraints and rejigging auxiliary counter enables
such that they only happen when FEAT_AMUv1p1 has been enabled so that's
more apparent.

Change-Id: I5b5061d603013598f07d70401d68915c016a1a1b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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