Ensure the flow through switch statements is clear

Ensure case clauses:
* Terminate with an unconditional break, return or goto statement.
* Use conditional break, return or goto statements as l

Ensure the flow through switch statements is clear

Ensure case clauses:
* Terminate with an unconditional break, return or goto statement.
* Use conditional break, return or goto statements as long as the end
of the case clause is unreachable; such case clauses must terminate
with assert(0) /* Unreachable */ or an unconditional __dead2 function
call
* Only fallthough when doing otherwise would result in less
readable/maintainable code; such case clauses must terminate with a
/* Fallthrough */ comment to make it clear this is the case and
indicate that a fallthrough is intended.

This reduces the chance of bugs appearing due to unintended flow through a
switch statement

Change-Id: I70fc2d1f4fd679042397dec12fd1982976646168
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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zynqmp: Define and enable ARM_XLAT_TABLES_LIB_V1

Enable ARM_XLAT_TABLES_LIB_V1 as ZynqMP is using
v1 library of translation tables.

With upstream patch d323af9e3d903d981b42f954844a95a6bfef91ab,
the

zynqmp: Define and enable ARM_XLAT_TABLES_LIB_V1

Enable ARM_XLAT_TABLES_LIB_V1 as ZynqMP is using
v1 library of translation tables.

With upstream patch d323af9e3d903d981b42f954844a95a6bfef91ab,
the usage of MAP_REGION_FLAT is referring to definition in file
include/lib/xlat_tables/xlat_tables_v2.h but while preparing
xlat tables in lib/xlat_tables/xlat_tables_common.c it is referring
to include/lib/xlat_tables/xlat_tables.h which is v1 xlat tables.
Also, ZynqMP was using v1 so defined ARM_XLAT_TABLES_LIB_V1 to
use v1 xlat tables everywhere.
This fixes the issue of xlat tables failures as it takes v2
library mmap_region structure in some files and v1 in other
files.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: Add ATF support for Data blob encryption and decryption

This patch adds ATF support for AES data blob encrypt/decrypt.
ATF establishes a path to send the address of the structure
to the xils

zynqmp: Add ATF support for Data blob encryption and decryption

This patch adds ATF support for AES data blob encrypt/decrypt.
ATF establishes a path to send the address of the structure
to the xilsecure, so that it will pick addresses of the data
and performs the requested operation (encrypt/decrypt) and puts
the result in load address.

where structure contains
- Data blob src address
- load address
- IV address
- Key address - this will actual key addr in case of KUP
else it will be zero.
- Data-size
- Aes-op type
- KeySrc

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: Remove emulation platform support

This patch removes support for emulation platforms
EP108 and Veloce.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

zynqmp: pm: Correct function header of clock APIs

Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will

zynqmp: pm: Correct function header of clock APIs

Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>

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zynqmp: pm_service: Ignore enable/disable of PLL type clocks

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

zynqmp: pm_service: Ignore enable/disable of PLL type clocks

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

Put PLL type clock into bypass and reset mode only while changing
PLL rate (FBDIV).

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: Add new API for pl configuration readback

This patch adds new API's for performing pl configuration
readback.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signe

zynqmp: Add new API for pl configuration readback

This patch adds new API's for performing pl configuration
readback.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: pm: Use critical flag instead of initenable

CCF has already provision to enable clock during registration
through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of
init_enable attribute.

zynqmp: pm: Use critical flag instead of initenable

CCF has already provision to enable clock during registration
through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of
init_enable attribute.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>

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zynqmp: pm: Correct WDT clock database

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL

zynqmp: pm: Correct WDT clock database

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>

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zynqmp: pm_service: Add support for writing to AFI registers

Add support for writing to AFI registers.
So that after writing a bitstream the interface can be programmed.

Signed-off-by: Shubhrajyoti

zynqmp: pm_service: Add support for writing to AFI registers

Add support for writing to AFI registers.
So that after writing a bitstream the interface can be programmed.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: pm: Add IOCTL to set boot health status

Since the MMIO read/write APIs are removed from Linux user space,
Linux cannot directly write to the Global General Storage Register 4
any more to set

zynqmp: pm: Add IOCTL to set boot health status

Since the MMIO read/write APIs are removed from Linux user space,
Linux cannot directly write to the Global General Storage Register 4
any more to set healthy boot status.

Create an IOCTL to allow Linux to set boot health status.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>

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zynqmp: pm_service: Add support for resetting ULPI transceiver

To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is be

zynqmp: pm_service: Add support for resetting ULPI transceiver

To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's
are controlled by BOOT_PIN_CTRL register present in CRL_APB
address region. Since CRL_APB can be resticted to secure access,
this pin should be controlled by ATF.

This patch adds the support for the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: pm: Add API to get number of clocks

Currently in Linux maximum number of clocks is hard-coded and
so it needs to allocate static memory. It can get actual clock
number after querying all clo

zynqmp: pm: Add API to get number of clocks

Currently in Linux maximum number of clocks is hard-coded and
so it needs to allocate static memory. It can get actual clock
number after querying all clock names by special clock name
string. Add new query data parameter to get actual number of
clocks so Linux can get actual clock numbers in advance.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>

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Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra

Fix several MISRA defects in PSCI library

Rework page table setup for varying number of mem regions

Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their co

Rework page table setup for varying number of mem regions

Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their coherent memory region doesn't contain anything and
therefore has a size of 0. Add check to ensure this
doesn't change without us knowing.

Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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PSCI: Fix types of definitions

Also change header guards to fix defects of MISRA C-2012 Rule 21.1.

Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>

PSCI: Fix types of definitions

Also change header guards to fix defects of MISRA C-2012 Rule 21.1.

Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1406 from robertovargas-arm/uuid

Make TF UUID RFC 4122 compliant

plat: xilinx: zynqmp: Get chipid from registers for BL32

This patch reads the chipid registers directly instead of making
pm call when running at BL32. User should ensure that these registers
should

plat: xilinx: zynqmp: Get chipid from registers for BL32

This patch reads the chipid registers directly instead of making
pm call when running at BL32. User should ensure that these registers
should always be accessed from APU in their system configuration.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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plat: xilinx: zynqmp: Build for DDR if SPD is enabled

This patch builds ATF to DDR if SPD is enabled as it cant fit in
On chip memory(OCM) with SPD enabled. This solves the issue
of build failure wi

plat: xilinx: zynqmp: Build for DDR if SPD is enabled

This patch builds ATF to DDR if SPD is enabled as it cant fit in
On chip memory(OCM) with SPD enabled. This solves the issue
of build failure with SPD enabled for ZynqMP platform.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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Make TF UUID RFC 4122 compliant

RFC4122 defines that fields are stored in network order (big endian),
but TF-A stores them in machine order (little endian by default in TF-A).
We cannot change the f

Make TF UUID RFC 4122 compliant

RFC4122 defines that fields are stored in network order (big endian),
but TF-A stores them in machine order (little endian by default in TF-A).
We cannot change the future UUIDs that are already generated, but we can store
all the bytes using arrays and modify fiptool to generate the UUIDs with
the correct byte order.

Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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zynqmp: Add wdt timeout restart functionality

This patch adds support to restart system incase of wdt
timeout.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

zynqmp: Fix EG/EV detection logic

The vcu disable bit in efuse ipdisable register is valid
only if PL powered up so, consider PL powerup status for
determing EG/EV part. If PL is not powered up, dis

zynqmp: Fix EG/EV detection logic

The vcu disable bit in efuse ipdisable register is valid
only if PL powered up so, consider PL powerup status for
determing EG/EV part. If PL is not powered up, display
EG/EV as a part of string. The PL powerup status will
be filled by pmufw based on PL PROGB status in the
9th bit of version field.This patch also used IPI
to get this info from pmufw instead of directly accessing
the registers. Accessing this info from pmufw using
IPI fixes the issue of PMUFW access denied error for
reading IPDISABLE register.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>

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zynqmp: Add new API for processing secure images

This patch adds new API for processing secure images. This API
is used for authentication and decryption of secure images using
xilsecure in pmufw.

zynqmp: Add new API for processing secure images

This patch adds new API for processing secure images. This API
is used for authentication and decryption of secure images using
xilsecure in pmufw.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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xilinx: zynqmp: pm_service: Fix APU only restart

Existing code blocks each IPI send request in ipi_mb_notify()
function till pmu clears respective bit in ipi observation
register.

After sending PM_

xilinx: zynqmp: pm_service: Fix APU only restart

Existing code blocks each IPI send request in ipi_mb_notify()
function till pmu clears respective bit in ipi observation
register.

After sending PM_SYSTEM_SHUTDOWN request to PMU, PMU will
restart APU. While PMU is restarting APU, ATF is running out
of OCM, which can cause read/write hang from/to OCM.
There is no need to wait for notification from PMU in case
of SystemShutdown request in ATF, as APU is going to restart.

This patch fixes APU only restart issue.

Signed-off-by: Tejas Patel <tejasp@xilinx.com>
Acked-by: Wendy Liang <wendy.liang@xilinx.com>

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plat: xilinx: zynqmp: Make fpga load blocking until completed

This patch makes bitstream load blocking call and waits until
bitstream is loaded successfully or return with error.

Signed-off-by: Siv

plat: xilinx: zynqmp: Make fpga load blocking until completed

This patch makes bitstream load blocking call and waits until
bitstream is loaded successfully or return with error.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Avesh Khan <aveshk@xilinx.com>

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