1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for pin control. 9 */ 10 11 #ifndef _PM_API_IOCTL_H_ 12 #define _PM_API_IOCTL_H_ 13 14 #include "pm_common.h" 15 16 //ioctl id 17 enum { 18 IOCTL_GET_RPU_OPER_MODE, 19 IOCTL_SET_RPU_OPER_MODE, 20 IOCTL_RPU_BOOT_ADDR_CONFIG, 21 IOCTL_TCM_COMB_CONFIG, 22 IOCTL_SET_TAPDELAY_BYPASS, 23 IOCTL_SET_SGMII_MODE, 24 IOCTL_SD_DLL_RESET, 25 IOCTL_SET_SD_TAPDELAY, 26 /* Ioctl for clock driver */ 27 IOCTL_SET_PLL_FRAC_MODE, 28 IOCTL_GET_PLL_FRAC_MODE, 29 IOCTL_SET_PLL_FRAC_DATA, 30 IOCTL_GET_PLL_FRAC_DATA, 31 IOCTL_WRITE_GGS, 32 IOCTL_READ_GGS, 33 IOCTL_WRITE_PGGS, 34 IOCTL_READ_PGGS, 35 /* IOCTL for ULPI reset */ 36 IOCTL_ULPI_RESET, 37 }; 38 39 //RPU operation mode 40 #define PM_RPU_MODE_LOCKSTEP 0U 41 #define PM_RPU_MODE_SPLIT 1U 42 43 //RPU boot mem 44 #define PM_RPU_BOOTMEM_LOVEC 0U 45 #define PM_RPU_BOOTMEM_HIVEC 1U 46 47 //RPU tcm mpde 48 #define PM_RPU_TCM_SPLIT 0U 49 #define PM_RPU_TCM_COMB 1U 50 51 //tap delay signal type 52 #define PM_TAPDELAY_NAND_DQS_IN 0U 53 #define PM_TAPDELAY_NAND_DQS_OUT 1U 54 #define PM_TAPDELAY_QSPI 2U 55 #define PM_TAPDELAY_MAX 3U 56 57 //tap delay bypass 58 #define PM_TAPDELAY_BYPASS_DISABLE 0U 59 #define PM_TAPDELAY_BYPASS_ENABLE 1U 60 61 //sgmii mode 62 #define PM_SGMII_DISABLE 0U 63 #define PM_SGMII_ENABLE 1U 64 65 enum tap_delay_type { 66 PM_TAPDELAY_INPUT, 67 PM_TAPDELAY_OUTPUT, 68 }; 69 70 //dll reset type 71 #define PM_DLL_RESET_ASSERT 0U 72 #define PM_DLL_RESET_RELEASE 1U 73 #define PM_DLL_RESET_PULSE 2U 74 75 enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, 76 unsigned int ioctl_id, 77 unsigned int arg1, 78 unsigned int arg2, 79 unsigned int *value); 80 #endif /* _PM_API_IOCTL_H_ */ 81