fix(qti): uart platform base address for SC7180

Following merge of [1] , SC7180 platform broke because of mismatched
UART base address. Restore to the proper value.

[1] https://review.trustedfirmwa

fix(qti): uart platform base address for SC7180

Following merge of [1] , SC7180 platform broke because of mismatched
UART base address. Restore to the proper value.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/43574/5/plat/qti/sc7180/inc/platform_def.h

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Change-Id: I4d34db01720ce289a87bccf0338205b4861e11cb

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feat(kodiak): add support for RB3Gen2 platform

RB3Gen2 is an IoT platform based on Kodiak SoC. Details about this
platform can be found here [1]. The boot flow with TF-A/OP-TEE is:

PBL (ROM) -> X

feat(kodiak): add support for RB3Gen2 platform

RB3Gen2 is an IoT platform based on Kodiak SoC. Details about this
platform can be found here [1]. The boot flow with TF-A/OP-TEE is:

PBL (ROM) -> XBL -> BL2 -> BL31 -> BL33 -> Normal world OS
|
--> BL32

Steps to build TF-A for RB3Gen2:

$ make -j`nproc` PLAT=rb3gen2 SPD=opteed QTISECLIB_PATH=<qtiseclib-path>
BL32=<path-to-optee-bin> BL33=<path-to-os-bootloader-bin> fip all

$ ./tools/qti/generate_fip_elf.sh build/rb3gen2/release/fip.bin 0x9fc00000

The resulting fip.elf should be flashed in uefi_a partition on UFS flash
storage.

Note here that the bl2.elf generated requires to be signed as TZ image
with QTI signing involved. There is an ongoing effort to enable OEM only
signing for future boards support.

[1] https://www.qualcomm.com/developer/hardware/rb3-gen-2-development-kit

Change-Id: Ic19f28a5f559a0da28337f2d8da0d0e289a94514
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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feat(qti): introduce basic XPU driver

Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.

Change-Id: I2b5ad50c

feat(qti): introduce basic XPU driver

Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.

Change-Id: I2b5ad50c57b0112302d3568e0e0bcf2116d3e259
Co-developed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): introduce SoC codename as Kodiak

Qualcomm has recently started using SoC codenames for upstream support
with Linux kernel being the first adoptor. Using SoC codenames for
upstream pro

refactor(qti): introduce SoC codename as Kodiak

Qualcomm has recently started using SoC codenames for upstream support
with Linux kernel being the first adoptor. Using SoC codenames for
upstream projects removes the need to follow different product names
like for kodiak which is also known as sc7280, qcm6490 etc.

Let's follow this practice of using SoC codenames for TF-A project too
beginning with Kodiak. While doing that let's refactor SoC and board
specific files where the existing support for sc7280 has been renamed to
sc7280_chrome to reflect it's usage.

Change-Id: I236fadf8ae9550f94deb05ebfed17e2ddbd69509
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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feat(qti): add TF-A BL2 common platform framework

Currently QTI pltforms only supports coreboot as the second stage
bootloader. Lets enable support for TF-A BL2 as the common reference
second stage

feat(qti): add TF-A BL2 common platform framework

Currently QTI pltforms only supports coreboot as the second stage
bootloader. Lets enable support for TF-A BL2 as the common reference
second stage bootloader which is able to support a variety of normal
world OS bootloaders (BL33) like edk2, U-Boot, coreboot-depthcharge etc.

The common reference boot flow should look like following on QTI
platforms:

PBL (ROM) -> XBL -> BL2 -> BL31 -> BL33 -> Normal world OS
|
--> BL32

As of now XBL is performing DRAM initialization and loads two set of
images for BL2 and FIP into DRAM from flash after performing secure boot
checks if enabled. Then BL2 does the FIP parsing from DRAM and loads
payloads at appropriate addresses as per the FIP configuration.

Note here that BL2 image is loaded from TZ partition on UFS flash which
by default requires QTI secure boot checks.

Change-Id: Ice73905bff39291fa417389cb84dabe455c3f0ba
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): refactor RNG as a proper driver

Refactor QTI RNG as a proper driver rather than being present in
platform code aligning with common practice followed by other platforms.

Change-Id: I

refactor(qti): refactor RNG as a proper driver

Refactor QTI RNG as a proper driver rather than being present in
platform code aligning with common practice followed by other platforms.

Change-Id: I4c1f23b7ea2f17fdb71792319b4c403db542b757
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC

Follow common practice to enable config option PLAT_XLAT_TABLES_DYNAMIC
via platform.mk instead of platform_def.h.

Change-Id: I18944d5b5e97d784195c6df3

fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC

Follow common practice to enable config option PLAT_XLAT_TABLES_DYNAMIC
via platform.mk instead of platform_def.h.

Change-Id: I18944d5b5e97d784195c6df374892029e24f3d0b
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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feat(qti): add BL32 support

Add support for loading a BL32 image like OP-TEE. In this case we stop
routing secure EL3 interrupts to EL3 and instead allow S-EL1 to handle
them.

Change-Id: I8ba25f83c

feat(qti): add BL32 support

Add support for loading a BL32 image like OP-TEE. In this case we stop
routing secure EL3 interrupts to EL3 and instead allow S-EL1 to handle
them.

Change-Id: I8ba25f83cfc8749974fb5760392a8c64b2cec18b
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): make UART config independent

Make UART configuration independent of coreboot since there are
alternative bootloaders like TF-A BL2 which can be supported. Also,
configure UART scope t

refactor(qti): make UART config independent

Make UART configuration independent of coreboot since there are
alternative bootloaders like TF-A BL2 which can be supported. Also,
configure UART scope to enable runtime logging as well.

Change-Id: I1956535c769c2c3141854d062dc02c289b86b48d
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): make CNTFRQ config independent

Make system counter frequency configuration independent of prior stage
boot-loader like coreboot to enable an alternative boot-loaders such as
TF-A BL2.

refactor(qti): make CNTFRQ config independent

Make system counter frequency configuration independent of prior stage
boot-loader like coreboot to enable an alternative boot-loaders such as
TF-A BL2.

Change-Id: Id22803557466643f6455a243929626f71a4714fc
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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fix(qti): fix build without coreboot

Skip some memory checks that rely on coreboot data.

Change-Id: I3c00aace547385af6b49632e3acfd9a977306a83
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.or

fix(qti): fix build without coreboot

Skip some memory checks that rely on coreboot data.

Change-Id: I3c00aace547385af6b49632e3acfd9a977306a83
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>

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refactor(platforms): remove usage of psci_power_down_wfi

The callers in PSCI will now call wfi() after calling the
pwr_domain_pwr_down() platform hook (previously they were mutually
exclusive). As s

refactor(platforms): remove usage of psci_power_down_wfi

The callers in PSCI will now call wfi() after calling the
pwr_domain_pwr_down() platform hook (previously they were mutually
exclusive). As such, there is no need for platforms to do this
themselves. In fact, it is strongly advisable for platforms not to do
this themselves so that the PSCI can apply any relevant errata
mitigations.

Change-Id: Ic9702edef7503996be24d984e29dfcc13bc3fcba
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(qti): allow secure r/w to the EUD enable register" into integration

fix(qti): allow secure r/w to the EUD enable register

The EUD (Embedded USB Debugger) is an IP block that can only be toggled
from the secure world. Allow accessing its enable register through the
S

fix(qti): allow secure r/w to the EUD enable register

The EUD (Embedded USB Debugger) is an IP block that can only be toggled
from the secure world. Allow accessing its enable register through the
SCM MMIO R/W calls.

The remaining (non-qtiseclib) platforms don't feature this hardware.

Compile-tested only, but should be simple enough.

Change-Id: I2763fd89f2a9d068ec2b4662dc2de91d1d466666
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

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fix: use LDLIBS instead of LDFLAGS for library search paths

The LDLIBS is quite convenient for both the -l and -L flags as both ld
and gcc will accept them identically when linking. So use LDLIBS an

fix: use LDLIBS instead of LDFLAGS for library search paths

The LDLIBS is quite convenient for both the -l and -L flags as both ld
and gcc will accept them identically when linking. So use LDLIBS and
leave LDFLAGS alone for flags that have some difference (eg needing a
-Wl prefix).

Change-Id: I3f2ab54931eff4e796dc4757950ed797ab3344a8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(msm8916): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensu

fix(msm8916): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensure compatibility with the updated TSP interface.

Change-Id: I2270a45f3f7a3d6f6dbc0ecd9f8a4fb56a6727f9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* cal

refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* calls.

Previously, EXTRA functions were individually implemented for
each SMCCC_ARCH_WORKAROUND_*, an approach that becomes unmanageable
with the increasing number of workarounds.
By looking up erratum entries for CVE check, the process is streamlined,
reducing overhead associated with creating and
maintaining EXTRA functions for each new workaround.

New Errata entries are created for SMC workarounds and
that is used to target cpus that are uniquely impacted
by SMC workarounds.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I873534e367a35c99461d0a616ff7bf856a0000af

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fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
e

chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
expectation so that future platform implementers don't get misled.

Change-Id: Ic33f0b6da74592ad6778fd802c2f0b85223af614
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor: panic after calling psci_power_down_wfi()

This function doesn't return and its callers that don't return either
rely on this. Drop the dead attribute and add a panic() after it to make
thi

refactor: panic after calling psci_power_down_wfi()

This function doesn't return and its callers that don't return either
rely on this. Drop the dead attribute and add a panic() after it to make
this expectation explicit. Calling `wfi` in the powerdown sequence is
terminal so even if the function was made to return, there would be no
functional change.

This is useful for a following patch that makes psci_power_down_wfi()
return.

Change-Id: I62ca1ee058b1eaeb046966c795081e01bf45a2eb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(qti): platform support for qcs615

Change-Id: Ibbe78a196d77530fa9d94d7d12b2f08a4b66d62e
Signed-off-by: Amarinder Singh Sethi <quic_assethi@quicinc.com>