1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <bl31/bl31.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/console.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/bl_aux_params/bl_aux_params.h> 16 #include <lib/coreboot.h> 17 #include <lib/spinlock.h> 18 19 #include <platform.h> 20 #include <qti_interrupt_svc.h> 21 #include <qti_plat.h> 22 #include <qti_uart_console.h> 23 #include <qtiseclib_interface.h> 24 25 /* Variable to hold QTI UART configuration */ 26 static console_t g_qti_console_uart; 27 28 /* 29 * Placeholder variables for copying the arguments that have been passed to 30 * BL31 from BL2. 31 */ 32 static entry_point_info_t bl33_image_ep_info; 33 34 /* 35 * Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot. 36 * Any other value means cold booted. 37 */ 38 uint32_t g_qti_bl31_cold_booted; 39 40 /******************************************************************************* 41 * Perform any BL31 early platform setup common to ARM standard platforms. 42 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 43 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 44 * done before the MMU is initialized so that the memory layout can be used 45 * while creating page tables. BL2 has flushed this information to memory, so 46 * we are guaranteed to pick up good data. 47 ******************************************************************************/ 48 void bl31_early_platform_setup(u_register_t from_bl2, 49 u_register_t plat_params_from_bl2) 50 { 51 bl_aux_params_parse(plat_params_from_bl2, NULL); 52 53 qti_console_uart_register(&g_qti_console_uart, PLAT_QTI_UART_BASE); 54 console_set_scope(&g_qti_console_uart, CONSOLE_FLAG_RUNTIME | 55 CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH); 56 /* 57 * Tell BL31 where the non-trusted software image 58 * is located and the entry state information 59 */ 60 bl31_params_parse_helper(from_bl2, NULL, &bl33_image_ep_info); 61 } 62 63 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 64 u_register_t arg2, u_register_t arg3) 65 { 66 bl31_early_platform_setup(arg0, arg1); 67 } 68 69 /******************************************************************************* 70 * Perform the very early platform specific architectural setup here. At the 71 * moment this only initializes the mmu in a quick and dirty way. 72 ******************************************************************************/ 73 void bl31_plat_arch_setup(void) 74 { 75 qti_setup_page_tables( 76 BL31_START, 77 BL31_END-BL31_START, 78 BL_CODE_BASE, 79 BL_CODE_END, 80 BL_RO_DATA_BASE, 81 BL_RO_DATA_END 82 ); 83 enable_mmu_el3(0); 84 } 85 86 /******************************************************************************* 87 * Perform any BL31 platform setup common to ARM standard platforms 88 ******************************************************************************/ 89 void bl31_platform_setup(void) 90 { 91 generic_delay_timer_init(); 92 /* Initialize the GIC driver, CPU and distributor interfaces */ 93 plat_qti_gic_driver_init(); 94 plat_qti_gic_init(); 95 qti_interrupt_svc_init(); 96 qtiseclib_bl31_platform_setup(); 97 98 /* set boot state to cold boot complete. */ 99 g_qti_bl31_cold_booted = 0x1; 100 } 101 102 /******************************************************************************* 103 * Return a pointer to the 'entry_point_info' structure of the next image for the 104 * security state specified. BL33 corresponds to the non-secure image type 105 * while BL32 corresponds to the secure image type. A NULL pointer is returned 106 * if the image does not exist. 107 ******************************************************************************/ 108 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 109 { 110 /* QTI platform don't have BL32 implementation. */ 111 assert(type == NON_SECURE); 112 assert(bl33_image_ep_info.h.type == PARAM_EP); 113 assert(bl33_image_ep_info.h.attr == NON_SECURE); 114 /* 115 * None of the images on the platforms can have 0x0 116 * as the entrypoint. 117 */ 118 if (bl33_image_ep_info.pc) { 119 return &bl33_image_ep_info; 120 } else { 121 return NULL; 122 } 123 } 124 125 /******************************************************************************* 126 * This function is used by the architecture setup code to retrieve the counter 127 * frequency for the CPU's generic timer. This value will be programmed into the 128 * CNTFRQ_EL0 register. In Arm standard platforms, it returns the base frequency 129 * of the system counter, which is retrieved from the first entry in the 130 * frequency modes table. This will be used later in warm boot (psci_arch_setup) 131 * of CPUs to set when CPU frequency. 132 ******************************************************************************/ 133 unsigned int plat_get_syscnt_freq2(void) 134 { 135 return PLAT_SYSCNT_FREQ; 136 } 137