1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <bl31/bl31.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/console.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/bl_aux_params/bl_aux_params.h> 16 #include <lib/coreboot.h> 17 #include <lib/spinlock.h> 18 19 #include <platform.h> 20 #include <qti_interrupt_svc.h> 21 #include <qti_plat.h> 22 #include <qti_uart_console.h> 23 #include <qtiseclib_interface.h> 24 25 /* 26 * Placeholder variables for copying the arguments that have been passed to 27 * BL31 from BL2. 28 */ 29 static entry_point_info_t bl33_image_ep_info; 30 31 /* 32 * Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot. 33 * Any other value means cold booted. 34 */ 35 uint32_t g_qti_bl31_cold_booted; 36 37 /******************************************************************************* 38 * Perform any BL31 early platform setup common to ARM standard platforms. 39 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 40 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 41 * done before the MMU is initialized so that the memory layout can be used 42 * while creating page tables. BL2 has flushed this information to memory, so 43 * we are guaranteed to pick up good data. 44 ******************************************************************************/ 45 void bl31_early_platform_setup(u_register_t from_bl2, 46 u_register_t plat_params_from_bl2) 47 { 48 bl_aux_params_parse(plat_params_from_bl2, NULL); 49 50 #if COREBOOT 51 if (coreboot_serial.baseaddr != 0) { 52 static console_t g_qti_console_uart; 53 54 qti_console_uart_register(&g_qti_console_uart, 55 coreboot_serial.baseaddr); 56 } 57 #endif 58 59 /* 60 * Tell BL31 where the non-trusted software image 61 * is located and the entry state information 62 */ 63 bl31_params_parse_helper(from_bl2, NULL, &bl33_image_ep_info); 64 } 65 66 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 67 u_register_t arg2, u_register_t arg3) 68 { 69 bl31_early_platform_setup(arg0, arg1); 70 } 71 72 /******************************************************************************* 73 * Perform the very early platform specific architectural setup here. At the 74 * moment this only initializes the mmu in a quick and dirty way. 75 ******************************************************************************/ 76 void bl31_plat_arch_setup(void) 77 { 78 qti_setup_page_tables( 79 BL31_START, 80 BL31_END-BL31_START, 81 BL_CODE_BASE, 82 BL_CODE_END, 83 BL_RO_DATA_BASE, 84 BL_RO_DATA_END 85 ); 86 enable_mmu_el3(0); 87 } 88 89 /******************************************************************************* 90 * Perform any BL31 platform setup common to ARM standard platforms 91 ******************************************************************************/ 92 void bl31_platform_setup(void) 93 { 94 generic_delay_timer_init(); 95 /* Initialize the GIC driver, CPU and distributor interfaces */ 96 plat_qti_gic_driver_init(); 97 plat_qti_gic_init(); 98 qti_interrupt_svc_init(); 99 qtiseclib_bl31_platform_setup(); 100 101 /* set boot state to cold boot complete. */ 102 g_qti_bl31_cold_booted = 0x1; 103 } 104 105 /******************************************************************************* 106 * Return a pointer to the 'entry_point_info' structure of the next image for the 107 * security state specified. BL33 corresponds to the non-secure image type 108 * while BL32 corresponds to the secure image type. A NULL pointer is returned 109 * if the image does not exist. 110 ******************************************************************************/ 111 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 112 { 113 /* QTI platform don't have BL32 implementation. */ 114 assert(type == NON_SECURE); 115 assert(bl33_image_ep_info.h.type == PARAM_EP); 116 assert(bl33_image_ep_info.h.attr == NON_SECURE); 117 /* 118 * None of the images on the platforms can have 0x0 119 * as the entrypoint. 120 */ 121 if (bl33_image_ep_info.pc) { 122 return &bl33_image_ep_info; 123 } else { 124 return NULL; 125 } 126 } 127 128 /******************************************************************************* 129 * This function is used by the architecture setup code to retrieve the counter 130 * frequency for the CPU's generic timer. This value will be programmed into the 131 * CNTFRQ_EL0 register. In Arm standard platforms, it returns the base frequency 132 * of the system counter, which is retrieved from the first entry in the 133 * frequency modes table. This will be used later in warm boot (psci_arch_setup) 134 * of CPUs to set when CPU frequency. 135 ******************************************************************************/ 136 unsigned int plat_get_syscnt_freq2(void) 137 { 138 return PLAT_SYSCNT_FREQ; 139 } 140