1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a520.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24workaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792 25 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(38) 26workaround_reset_end cortex_a520, ERRATUM(2630792) 27 28check_erratum_ls cortex_a520, ERRATUM(2630792), CPU_REV(0, 1) 29 30workaround_reset_start cortex_a520, ERRATUM(2858100), ERRATA_A520_2858100 31 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(29) 32workaround_reset_end cortex_a520, ERRATUM(2858100) 33 34check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1) 35 /* ---------------------------------------------------- 36 * HW will do the cache maintenance while powering down 37 * ---------------------------------------------------- 38 */ 39func cortex_a520_core_pwr_dwn 40 /* --------------------------------------------------- 41 * Enable CPU power down bit in power control register 42 * --------------------------------------------------- 43 */ 44 sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 45 isb 46 ret 47endfunc cortex_a520_core_pwr_dwn 48 49cpu_reset_func_start cortex_a520 50 /* Disable speculative loads */ 51 msr SSBS, xzr 52cpu_reset_func_end cortex_a520 53 54 /* --------------------------------------------- 55 * This function provides Cortex A520 specific 56 * register information for crash reporting. 57 * It needs to return with x6 pointing to 58 * a list of register names in ascii and 59 * x8 - x15 having values of registers to be 60 * reported. 61 * --------------------------------------------- 62 */ 63.section .rodata.cortex_a520_regs, "aS" 64cortex_a520_regs: /* The ascii list of register names to be reported */ 65 .asciz "cpuectlr_el1", "" 66 67func cortex_a520_cpu_reg_dump 68 adr x6, cortex_a520_regs 69 mrs x8, CORTEX_A520_CPUECTLR_EL1 70 ret 71endfunc cortex_a520_cpu_reg_dump 72 73declare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \ 74 cortex_a520_reset_func, \ 75 cortex_a520_core_pwr_dwn 76