feat(qemu-sbsa): support s-el2 and s-el1 spmc

Reserve memory for TB_FW_CONFIG and TOS_FW_CONFIG if configured with
SPD=spmd and optionally SPMD_SPM_AT_SEL2=1.

Change-Id: I2f27502b6d5f9f0131ab8ba273

feat(qemu-sbsa): support s-el2 and s-el1 spmc

Reserve memory for TB_FW_CONFIG and TOS_FW_CONFIG if configured with
SPD=spmd and optionally SPMD_SPM_AT_SEL2=1.

Change-Id: I2f27502b6d5f9f0131ab8ba273ab738de5643d45
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

Merge "feat(qemu): add hob support for qemu platforms" into integration

fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks

fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks, allocate a static array and pass its address to
gpt_runtime_init(). This frees up a little bit of space formerly
reserved for alignment of the GPT.

Change-Id: I48a1a2bc230f64e13e3ed08b18ebdc2d387d77d0
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

show more ...

feat(qemu): add hob support for qemu platforms

This change introduces the hob support for both qemu platforms (virt and
sbsa).

As the hob list feature relies on transfer list, the transfer list
sup

feat(qemu): add hob support for qemu platforms

This change introduces the hob support for both qemu platforms (virt and
sbsa).

As the hob list feature relies on transfer list, the transfer list
support is promoted to common qemu build configuration. The platforms
specific definitions are updated accordingly.

Change-Id: I473d83388fe95408d34515bf7bcbdd64ce4e777d
Signed-off-by: Kun Qin <kuqin@microsoft.com>

show more ...

feat(qemu-sbsa): add support for RME on SBSA machine

Add the necessary foundation to support Arm's RME extension on the SBSA
reference architecture.

Change-Id: If5a63ed0015cb33fcae367ff2cded811bbdc

feat(qemu-sbsa): add support for RME on SBSA machine

Add the necessary foundation to support Arm's RME extension on the SBSA
reference architecture.

Change-Id: If5a63ed0015cb33fcae367ff2cded811bbdc1e54
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE

When RME is enabled the RMM is placed at the bottom of the NS RAM,
meaning that NS_DRAM0_BASE has to be located after that.

This

feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE

When RME is enabled the RMM is placed at the bottom of the NS RAM,
meaning that NS_DRAM0_BASE has to be located after that.

This patch disscociates the base of the NS RAM as defined by QEMU by
introducing a new define, PLAT_QEMU_DRAM0_BASE. An offset can be added
to that new define when the software's view of the base memory need to
differ from QEMU.

No change in functionality.

Change-Id: I887f9993d5a61896352cfff17e0d92e2c2b9030a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

feat(qemu-sbsa): increase maximum FIP size

Following what was done for:

f465ac221001 ("fix(qemu): increase max FIP size")

increase the size of the FIP image to take up the remaining
space in FLASH

feat(qemu-sbsa): increase maximum FIP size

Following what was done for:

f465ac221001 ("fix(qemu): increase max FIP size")

increase the size of the FIP image to take up the remaining
space in FLASH0. That way the RMM image can also be added
to the FIP.

Change-Id: I89bba36f751468e99241f1c20b51c48fe06d8229
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

refactor(qemu-sbsa): create accessor functions for platform info

Creating accessor functions to access information held by struct
qemu_platform_info. That way the code that is relevant to fetching
i

refactor(qemu-sbsa): create accessor functions for platform info

Creating accessor functions to access information held by struct
qemu_platform_info. That way the code that is relevant to fetching
information from the device tree can be taken out of sbsa_sip_svc.c and
placed in a file where other client can use the information it provides.

No change in functionality.

Change-Id: I989952ee6d15e1436549002dd7c7767c745ea297
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful

There is no relation between the name of function sip_svc_init() and
what it does. As such rename it to something mo

refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful

There is no relation between the name of function sip_svc_init() and
what it does. As such rename it to something more appropriate and move
it to a header that make sense.

No change in functionality.

Change-Id: I7bd78b1fe70e2930c395ef0a097bfad3b1e55d3a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

refactor(qemu-sbsa): move DT related structures to their own header

Move structure declaration related to the DT to their own header. That
way they can be reused by other files. At the same time,

refactor(qemu-sbsa): move DT related structures to their own header

Move structure declaration related to the DT to their own header. That
way they can be reused by other files. At the same time, typedefs are
removed and structure names prepended with "platform_" to avoid clashing
with other structure declarations available in the system.

No change in functionality.

Change-Id: If67a141cc7441b0636af774d7edfe51cf8034a11
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPD

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
> and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
> In Armv8.6, the architecture standardized this frequency to 1GHz.

This change stops TF-A from hardcoding 62.5MHz frequency. Instead value
stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older
cores and 1GHz on newer ones.

Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

show more ...