1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <bpmp_ipc.h> 14 #include <common/debug.h> 15 #include <drivers/delay_timer.h> 16 #include <lib/mmio.h> 17 #include <lib/psci/psci.h> 18 #include <tegra_platform.h> 19 20 #include "se_private.h" 21 22 /******************************************************************************* 23 * Constants and Macros 24 ******************************************************************************/ 25 #define ERR_STATUS_SW_CLEAR U(0xFFFFFFFF) 26 #define INT_STATUS_SW_CLEAR U(0xFFFFFFFF) 27 #define MAX_TIMEOUT_MS U(100) /* Timeout in 100ms */ 28 #define NUM_SE_REGS_TO_SAVE U(4) 29 30 /******************************************************************************* 31 * Data structure and global variables 32 ******************************************************************************/ 33 static uint32_t se_regs[NUM_SE_REGS_TO_SAVE]; 34 35 /* 36 * Check that SE operation has completed after kickoff. 37 * 38 * This function is invoked after an SE operation has been started, 39 * and it checks the following conditions: 40 * 41 * 1. SE_STATUS = IDLE 42 * 2. AHB bus data transfer is complete. 43 * 3. SE_ERR_STATUS is clean. 44 */ 45 static bool tegra_se_is_operation_complete(void) 46 { 47 uint32_t val = 0, timeout = 0, sha_status, aes_status; 48 int32_t ret = 0; 49 bool se_is_busy, txn_has_errors, txn_successful; 50 51 /* 52 * Poll the status register to check if the operation 53 * completed. 54 */ 55 do { 56 val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS); 57 se_is_busy = !!(val & CTX_SAVE_AUTO_SE_BUSY); 58 59 /* sleep until SE finishes */ 60 if (se_is_busy) { 61 mdelay(1); 62 timeout++; 63 } 64 65 } while (se_is_busy && (timeout < MAX_TIMEOUT_MS)); 66 67 /* any transaction errors? */ 68 txn_has_errors = (tegra_se_read_32(SHA_ERR_STATUS) != 0U) || 69 (tegra_se_read_32(AES0_ERR_STATUS) != 0U); 70 71 /* transaction successful? */ 72 sha_status = tegra_se_read_32(SHA_INT_STATUS) & SHA_SE_OP_DONE; 73 aes_status = tegra_se_read_32(AES0_INT_STATUS) & AES0_SE_OP_DONE; 74 txn_successful = (sha_status == SHA_SE_OP_DONE) && 75 (aes_status == AES0_SE_OP_DONE); 76 77 if ((timeout == MAX_TIMEOUT_MS) || txn_has_errors || !txn_successful) { 78 ERROR("%s: Atomic context save operation failed!\n", 79 __func__); 80 ret = -ECANCELED; 81 } 82 83 return (ret == 0); 84 } 85 86 /* 87 * Wait for SE engine to be idle and clear any pending interrupts, before 88 * starting the next SE operation. 89 */ 90 static bool tegra_se_is_ready(void) 91 { 92 int32_t ret = 0; 93 uint32_t val = 0, timeout = 0; 94 bool se_is_ready; 95 96 /* Wait for previous operation to finish */ 97 do { 98 val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS); 99 se_is_ready = (val == CTX_SAVE_AUTO_SE_READY); 100 101 /* sleep until SE is ready */ 102 if (!se_is_ready) { 103 mdelay(1); 104 timeout++; 105 } 106 107 } while (!se_is_ready && (timeout < MAX_TIMEOUT_MS)); 108 109 if (timeout == MAX_TIMEOUT_MS) { 110 ERROR("%s: SE is not ready!\n", __func__); 111 ret = -ETIMEDOUT; 112 } 113 114 /* Clear any pending interrupts from previous operation */ 115 tegra_se_write_32(AES0_INT_STATUS, INT_STATUS_SW_CLEAR); 116 tegra_se_write_32(AES1_INT_STATUS, INT_STATUS_SW_CLEAR); 117 tegra_se_write_32(RSA_INT_STATUS, INT_STATUS_SW_CLEAR); 118 tegra_se_write_32(SHA_INT_STATUS, INT_STATUS_SW_CLEAR); 119 120 /* Clear error status for each engine seen from current port */ 121 tegra_se_write_32(AES0_ERR_STATUS, ERR_STATUS_SW_CLEAR); 122 tegra_se_write_32(AES1_ERR_STATUS, ERR_STATUS_SW_CLEAR); 123 tegra_se_write_32(RSA_ERR_STATUS, ERR_STATUS_SW_CLEAR); 124 tegra_se_write_32(SHA_ERR_STATUS, ERR_STATUS_SW_CLEAR); 125 126 return (ret == 0); 127 } 128 129 /* 130 * During System Suspend, this handler triggers the hardware context 131 * save operation. 132 */ 133 static int32_t tegra_se_save_context(void) 134 { 135 int32_t ret = -ECANCELED; 136 137 /* 138 * 1. Ensure all SE Driver including RNG1/PKA1 are shut down. 139 * TSEC/R5s are powergated/idle. All tasks on SE1~SE4, RNG1, 140 * PKA1 are wrapped up. SE0 is ready for use. 141 * 2. Clear interrupt/error in SE0 status register. 142 * 3. Scrub SE0 register to avoid false failure for illegal 143 * configuration. Probably not needed, dependent on HW 144 * implementation. 145 * 4. Check SE is ready for HW CTX_SAVE by polling 146 * SE_CTX_SAVE_AUTO_STATUS.SE_READY. 147 * 148 * Steps 1-4 are executed by tegra_se_is_ready(). 149 * 150 * 5. Issue context save command. 151 * 6. Check SE is busy with CTX_SAVE, the command in step5 was not 152 * dropped for ongoing traffic in any of SE port/engine. 153 * 7. Poll SE register or wait for SE APB interrupt for task completion 154 * a. Polling: Read SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE 155 * b. Interrupt: After receiving interrupt from SE APB, read 156 * SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE. 157 * 8. Check AES0 and SHA ERR_STATUS to ensure no error case. 158 * 9. Check AES0 and SHA INT_STATUS to ensure operation has successfully 159 * completed. 160 * 161 * Steps 6-9 are executed by tegra_se_is_operation_complete(). 162 */ 163 if (tegra_se_is_ready()) { 164 165 /* Issue context save command */ 166 tegra_se_write_32(AES0_OPERATION, SE_OP_CTX_SAVE); 167 168 /* Wait for operation to finish */ 169 if (tegra_se_is_operation_complete()) { 170 ret = 0; 171 } 172 } 173 174 return ret; 175 } 176 177 /* 178 * Handler to power down the SE hardware blocks - SE, RNG1 and PKA1. This 179 * needs to be called only during System Suspend. 180 */ 181 int32_t tegra_se_suspend(void) 182 { 183 int32_t ret = 0; 184 185 /* initialise communication channel with BPMP */ 186 assert(tegra_bpmp_ipc_init() == 0); 187 188 /* Enable SE clock before SE context save */ 189 tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); 190 191 /* save SE registers */ 192 se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT); 193 se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL); 194 se_regs[2] = mmio_read_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT); 195 se_regs[3] = mmio_read_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT); 196 197 /* Save SE context. The BootROM restores it during System Resume */ 198 ret = tegra_se_save_context(); 199 if (ret != 0) { 200 ERROR("%s: context save failed (%d)\n", __func__, ret); 201 } 202 203 /* Disable SE clock after SE context save */ 204 tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); 205 206 return ret; 207 } 208 209 /* 210 * Handler to power up the SE hardware block(s) during System Resume. 211 */ 212 void tegra_se_resume(void) 213 { 214 /* initialise communication channel with BPMP */ 215 assert(tegra_bpmp_ipc_init() == 0); 216 217 /* Enable SE clock before SE context restore */ 218 tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); 219 220 /* 221 * When TZ takes over after System Resume, TZ should first reconfigure 222 * SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT, 223 * RNG1_MUTEX_WATCHDOG_NS_LIMIT and SE_ENTROPY_SRC_AGE_CTRL before 224 * other operations. 225 */ 226 mmio_write_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT, se_regs[0]); 227 mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]); 228 mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]); 229 mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]); 230 231 /* Disable SE clock after SE context restore */ 232 tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); 233 } 234