1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2019-2020, Linaro Limited and Contributors. 4 * All rights reserved. 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 #include <tbbr_img_def.h> 13 14 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16 17 #define PLATFORM_STACK_SIZE 0x1000 18 19 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 20 /* 21 * Define the number of cores per cluster used in calculating core position. 22 * The cluster number is shifted by this value and added to the core ID, 23 * so its value represents log2(cores/cluster). 24 * Default is 2**(3) = 8 cores per cluster. 25 */ 26 #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(3) 27 #define PLATFORM_CLUSTER_COUNT U(64) 28 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 29 PLATFORM_MAX_CPUS_PER_CLUSTER) 30 #define QEMU_PRIMARY_CPU U(0) 31 32 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 33 PLATFORM_CORE_COUNT) 34 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 35 36 #define PLAT_MAX_RET_STATE 1 37 #define PLAT_MAX_OFF_STATE 2 38 39 /* Local power state for power domains in Run state. */ 40 #define PLAT_LOCAL_STATE_RUN 0 41 /* Local power state for retention. Valid only for CPU power domains */ 42 #define PLAT_LOCAL_STATE_RET 1 43 /* 44 * Local power state for OFF/power-down. Valid for CPU and cluster power 45 * domains. 46 */ 47 #define PLAT_LOCAL_STATE_OFF 2 48 49 /* 50 * Macros used to parse state information from State-ID if it is using the 51 * recommended encoding for State-ID. 52 */ 53 #define PLAT_LOCAL_PSTATE_WIDTH 4 54 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 55 56 /* 57 * Some data must be aligned on the biggest cache line size in the platform. 58 * This is known only to the platform as it might have a combination of 59 * integrated and external caches. 60 */ 61 #define CACHE_WRITEBACK_SHIFT 6 62 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 63 64 /* 65 * Define the max number of memory nodes. 66 */ 67 #define PLAT_MAX_MEM_NODES 128 68 69 /* Where QEMU starts the NS RAM */ 70 #define PLAT_QEMU_DRAM0_BASE 0x10000000000ULL 71 72 /* 73 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 74 * and secure DRAM. 75 */ 76 #define SEC_ROM_BASE 0x00000000 77 #define SEC_ROM_SIZE 0x00020000 78 79 /* 80 * When the RME extension is enabled, the base of the NS RAM is shifted after 81 * RMM. 82 */ 83 #define NS_DRAM0_BASE (PLAT_QEMU_DRAM0_BASE + \ 84 NS_DRAM0_BASE_OFFSET) 85 #define NS_DRAM0_SIZE 0x00020000000 86 87 #define SEC_SRAM_BASE 0x20000000 88 #define SEC_SRAM_SIZE 0x20000000 89 90 /* 91 * RAD just placeholders, need to be chosen after finalizing mem map 92 */ 93 #define SEC_DRAM_BASE 0x1000 94 #define SEC_DRAM_SIZE 0x1000 95 96 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 97 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 98 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 99 100 /* 101 * ARM-TF lives in SRAM, partition it here 102 */ 103 104 #define SHARED_RAM_BASE SEC_SRAM_BASE 105 #define SHARED_RAM_SIZE 0x00002000 106 107 #define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 108 #define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) 109 #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) 110 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 111 PLAT_QEMU_HOLD_ENTRY_SIZE) 112 #define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 113 #define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) 114 #define PLAT_QEMU_HOLD_STATE_WAIT 0 115 #define PLAT_QEMU_HOLD_STATE_GO 1 116 117 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 118 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 119 120 /* 121 * BL1 specific defines. 122 * 123 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 124 * addresses. 125 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 126 * the current BL1 RW debug size plus a little space for growth. 127 */ 128 #define BL1_SIZE 0x12000 129 #define BL1_RO_BASE SEC_ROM_BASE 130 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 131 #define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE) 132 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 133 134 /* 135 * BL2 specific defines. 136 * 137 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 138 * size plus a little space for growth. 139 */ 140 #define BL2_SIZE 0x1D000 141 #define BL2_BASE (BL31_BASE - BL2_SIZE) 142 #define BL2_LIMIT BL31_BASE 143 144 /* 145 * BL3-1 specific defines. 146 * 147 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 148 * current BL3-1 debug size plus a little space for growth. 149 */ 150 #define BL31_SIZE 0x300000 151 #define BL31_BASE (BL31_LIMIT - BL31_SIZE) 152 #define BL31_LIMIT (BL1_RW_BASE) 153 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 154 155 156 /* 157 * BL3-2 specific defines. 158 * 159 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 160 */ 161 #define BL32_SRAM_BASE BL_RAM_BASE 162 #define BL32_SRAM_LIMIT BL2_BASE 163 164 #define BL32_MEM_BASE BL_RAM_BASE 165 #define BL32_MEM_SIZE (BL_RAM_SIZE - BL1_SIZE - \ 166 BL2_SIZE - BL31_SIZE) 167 #define BL32_BASE BL32_SRAM_BASE 168 #define BL32_LIMIT BL32_SRAM_LIMIT 169 170 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) 171 #define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) 172 173 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42) 174 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42) 175 #if SPM_MM 176 #define MAX_MMAP_REGIONS 12 177 #define MAX_XLAT_TABLES 12 178 #else 179 #define MAX_MMAP_REGIONS 11 180 #define MAX_XLAT_TABLES 11 181 #endif 182 #define MAX_IO_DEVICES 3 183 #define MAX_IO_HANDLES 4 184 185 #if SPM_MM && defined(IMAGE_BL31) 186 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 187 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 50 188 #endif 189 190 /* 191 * PL011 related constants 192 */ 193 #define UART0_BASE 0x60000000 194 #define UART1_BASE 0x60030000 195 #define UART0_CLK_IN_HZ 1 196 #define UART1_CLK_IN_HZ 1 197 198 /* Secure UART */ 199 #define UART2_BASE 0x60040000 200 #define UART2_CLK_IN_HZ 1 201 202 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 203 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 204 205 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 206 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 207 208 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 209 210 #define QEMU_FLASH0_BASE 0x00000000 211 #define QEMU_FLASH0_SIZE 0x10000000 212 #define QEMU_FLASH1_BASE 0x10000000 213 #define QEMU_FLASH1_SIZE 0x10000000 214 215 #define PLAT_QEMU_FIP_BASE BL1_SIZE 216 #define PLAT_QEMU_FIP_MAX_SIZE (QEMU_FLASH0_SIZE - BL1_SIZE) 217 218 /* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */ 219 #define DEVICE0_BASE 0x40000000 220 #define DEVICE0_SIZE 0x04080000 221 /* This is map from NORMAL_UART up to SECURE_UART_MM */ 222 #define DEVICE1_BASE 0x60000000 223 #define DEVICE1_SIZE 0x10041000 224 /* This is a map for SECURE_EC */ 225 #define DEVICE2_BASE 0x50000000 226 #define DEVICE2_SIZE 0x00001000 227 228 /* 229 * GIC related constants 230 * We use GICv3 where CPU Interface registers are not memory mapped 231 * 232 * Legacy values - on platform version 0.1+ they are read from DT 233 */ 234 #define GICD_BASE 0x40060000 235 #define GICR_BASE 0x40080000 236 #define GICC_BASE 0x0 237 238 #define QEMU_IRQ_SEC_SGI_0 8 239 #define QEMU_IRQ_SEC_SGI_1 9 240 #define QEMU_IRQ_SEC_SGI_2 10 241 #define QEMU_IRQ_SEC_SGI_3 11 242 #define QEMU_IRQ_SEC_SGI_4 12 243 #define QEMU_IRQ_SEC_SGI_5 13 244 #define QEMU_IRQ_SEC_SGI_6 14 245 #define QEMU_IRQ_SEC_SGI_7 15 246 247 /****************************************************************************** 248 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 249 * interrupts. 250 *****************************************************************************/ 251 #define PLATFORM_G1S_PROPS(grp) \ 252 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 253 grp, GIC_INTR_CFG_EDGE), \ 254 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 255 grp, GIC_INTR_CFG_EDGE), \ 256 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 257 grp, GIC_INTR_CFG_EDGE), \ 258 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 259 grp, GIC_INTR_CFG_EDGE), \ 260 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 261 grp, GIC_INTR_CFG_EDGE), \ 262 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 263 grp, GIC_INTR_CFG_EDGE), \ 264 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 265 grp, GIC_INTR_CFG_EDGE), \ 266 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 267 grp, GIC_INTR_CFG_EDGE) 268 269 #define PLATFORM_G0_PROPS(grp) 270 271 /* 272 * DT related constants 273 */ 274 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 275 #define PLAT_QEMU_DT_MAX_SIZE 0x100000 276 277 #if SPM_MM 278 #define PLAT_QEMU_SP_IMAGE_BASE BL_RAM_BASE 279 #define PLAT_QEMU_SP_IMAGE_SIZE ULL(0x300000) 280 281 #ifdef IMAGE_BL2 282 /* In BL2 all memory allocated to the SPM Payload image is marked as RW. */ 283 # define QEMU_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 284 PLAT_QEMU_SP_IMAGE_BASE, \ 285 PLAT_QEMU_SP_IMAGE_SIZE, \ 286 MT_MEMORY | MT_RW | \ 287 MT_SECURE) 288 #elif IMAGE_BL31 289 /* All SPM Payload memory is marked as code in S-EL0 */ 290 # define QEMU_SP_IMAGE_MMAP MAP_REGION2(PLAT_QEMU_SP_IMAGE_BASE, \ 291 PLAT_QEMU_SP_IMAGE_BASE, \ 292 PLAT_QEMU_SP_IMAGE_SIZE, \ 293 MT_CODE | MT_SECURE | \ 294 MT_USER, \ 295 PAGE_SIZE) 296 #endif 297 298 /* 299 * EL3 -> S-EL0 secure shared memory 300 */ 301 #define PLAT_SPM_BUF_PCPU_SIZE ULL(0x10000) 302 #define PLAT_SPM_BUF_SIZE (PLATFORM_CORE_COUNT * \ 303 PLAT_SPM_BUF_PCPU_SIZE) 304 #define PLAT_SPM_BUF_BASE (BL32_LIMIT - PLAT_SPM_BUF_SIZE) 305 306 #define QEMU_SPM_BUF_EL3_MMAP MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, \ 307 PLAT_SPM_BUF_SIZE, \ 308 MT_RW_DATA | MT_SECURE) 309 310 #define QEMU_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \ 311 PLAT_SPM_BUF_BASE, \ 312 PLAT_SPM_BUF_SIZE, \ 313 MT_RO_DATA | MT_SECURE | \ 314 MT_USER, \ 315 PAGE_SIZE) 316 317 /* 318 * Shared memory between Normal world and S-EL0 for 319 * passing data during service requests. It will be marked as RW and NS. 320 * This buffer is allocated at the top of NS_DRAM, the base address is 321 * overridden in SPM initialization. 322 */ 323 #define PLAT_QEMU_SP_IMAGE_NS_BUF_BASE (PLAT_QEMU_DT_BASE + \ 324 PLAT_QEMU_DT_MAX_SIZE) 325 #define PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE ULL(0x200000) 326 327 #define QEMU_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 328 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 329 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 330 PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE, \ 331 MT_RW_DATA | MT_NS | \ 332 MT_USER, \ 333 PAGE_SIZE) 334 335 #define PLAT_SP_IMAGE_NS_BUF_BASE PLAT_QEMU_SP_IMAGE_NS_BUF_BASE 336 #define PLAT_SP_IMAGE_NS_BUF_SIZE PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE 337 338 #define PLAT_QEMU_SP_IMAGE_HEAP_BASE (PLAT_QEMU_SP_IMAGE_BASE + \ 339 PLAT_QEMU_SP_IMAGE_SIZE) 340 #define PLAT_QEMU_SP_IMAGE_HEAP_SIZE ULL(0x800000) 341 342 #define PLAT_SP_IMAGE_STACK_BASE (PLAT_QEMU_SP_IMAGE_HEAP_BASE + \ 343 PLAT_QEMU_SP_IMAGE_HEAP_SIZE) 344 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000) 345 #define QEMU_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 346 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 347 348 #define QEMU_SP_IMAGE_RW_MMAP MAP_REGION2( \ 349 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 350 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 351 (QEMU_SP_IMAGE_STACK_TOTAL_SIZE + \ 352 PLAT_QEMU_SP_IMAGE_HEAP_SIZE), \ 353 MT_RW_DATA | MT_SECURE | \ 354 MT_USER, \ 355 PAGE_SIZE) 356 357 /* 358 * Secure variable storage is located at Secure Flash. 359 */ 360 #if SPM_MM 361 #define QEMU_SECURE_VARSTORE_BASE 0x01000000 362 #define QEMU_SECURE_VARSTORE_SIZE 0x00100000 363 #define MAP_SECURE_VARSTORE MAP_REGION_FLAT( \ 364 QEMU_SECURE_VARSTORE_BASE, \ 365 QEMU_SECURE_VARSTORE_SIZE, \ 366 MT_DEVICE | MT_RW | \ 367 MT_SECURE | MT_USER) 368 #endif 369 370 /* Total number of memory regions with distinct properties */ 371 #define PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS 6 372 373 /* 374 * Name of the section to put the translation tables used by the S-EL1/S-EL0 375 * context of a Secure Partition. 376 */ 377 #define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" 378 #define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" 379 380 /* Cookies passed to the Secure Partition at boot. Not used by QEMU platforms.*/ 381 #define PLAT_SPM_COOKIE_0 ULL(0) 382 #define PLAT_SPM_COOKIE_1 ULL(0) 383 #endif 384 385 #define QEMU_PRI_BITS 2 386 #define PLAT_SP_PRI 0x20 387 388 #define NS_DRAM0_BASE_OFFSET 0 389 390 #endif /* PLATFORM_DEF_H */ 391