1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_boot_device.h> 27 #include <stm32mp1_dbgmcu.h> 28 #include <stm32mp1_private.h> 29 #endif 30 31 /******************************************************************************* 32 * CHIP ID 33 ******************************************************************************/ 34 #define STM32MP157C_PART_NB U(0x05000000) 35 #define STM32MP157A_PART_NB U(0x05000001) 36 #define STM32MP153C_PART_NB U(0x05000024) 37 #define STM32MP153A_PART_NB U(0x05000025) 38 #define STM32MP151C_PART_NB U(0x0500002E) 39 #define STM32MP151A_PART_NB U(0x0500002F) 40 41 #define STM32MP1_REV_B U(0x2000) 42 43 /******************************************************************************* 44 * PACKAGE ID 45 ******************************************************************************/ 46 #define PKG_AA_LFBGA448 U(4) 47 #define PKG_AB_LFBGA354 U(3) 48 #define PKG_AC_TFBGA361 U(2) 49 #define PKG_AD_TFBGA257 U(1) 50 51 /******************************************************************************* 52 * STM32MP1 memory map related constants 53 ******************************************************************************/ 54 #define STM32MP_ROM_BASE U(0x00000000) 55 #define STM32MP_ROM_SIZE U(0x00020000) 56 57 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 58 #define STM32MP_SYSRAM_SIZE U(0x00040000) 59 60 /* DDR configuration */ 61 #define STM32MP_DDR_BASE U(0xC0000000) 62 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 63 #ifdef AARCH32_SP_OPTEE 64 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 65 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 66 #endif 67 68 /* DDR power initializations */ 69 #ifndef __ASSEMBLER__ 70 enum ddr_type { 71 STM32MP_DDR3, 72 STM32MP_LPDDR2, 73 STM32MP_LPDDR3 74 }; 75 #endif 76 77 /* Section used inside TF binaries */ 78 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 79 /* 256 Octets reserved for header */ 80 #define STM32MP_HEADER_SIZE U(0x00000100) 81 82 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 83 STM32MP_PARAM_LOAD_SIZE + \ 84 STM32MP_HEADER_SIZE) 85 86 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 87 (STM32MP_PARAM_LOAD_SIZE + \ 88 STM32MP_HEADER_SIZE)) 89 90 #ifdef AARCH32_SP_OPTEE 91 #define STM32MP_BL32_SIZE U(0) 92 93 #define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE 94 95 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 96 STM32MP_OPTEE_BASE) 97 #else 98 #if STACK_PROTECTOR_ENABLED 99 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */ 100 #else 101 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */ 102 #endif 103 #endif 104 105 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 106 STM32MP_SYSRAM_SIZE - \ 107 STM32MP_BL32_SIZE) 108 109 #ifdef AARCH32_SP_OPTEE 110 #if STACK_PROTECTOR_ENABLED 111 #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */ 112 #else 113 #define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */ 114 #endif 115 #else 116 #if STACK_PROTECTOR_ENABLED 117 #define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */ 118 #else 119 #define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */ 120 #endif 121 #endif 122 123 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 124 STM32MP_BL2_SIZE) 125 126 /* BL2 and BL32/sp_min require 4 tables */ 127 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 128 129 /* 130 * MAX_MMAP_REGIONS is usually: 131 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 132 */ 133 #if defined(IMAGE_BL2) 134 #define MAX_MMAP_REGIONS 11 135 #endif 136 #if defined(IMAGE_BL32) 137 #define MAX_MMAP_REGIONS 6 138 #endif 139 140 /* DTB initialization value */ 141 #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 142 143 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 144 STM32MP_DTB_SIZE) 145 146 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 147 148 /* Define maximum page size for NAND devices */ 149 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 150 151 /******************************************************************************* 152 * STM32MP1 RAW partition offset for MTD devices 153 ******************************************************************************/ 154 #define STM32MP_NOR_BL33_OFFSET U(0x00080000) 155 #ifdef AARCH32_SP_OPTEE 156 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) 157 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) 158 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) 159 #endif 160 161 #define STM32MP_NAND_BL33_OFFSET U(0x00200000) 162 #ifdef AARCH32_SP_OPTEE 163 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) 164 #define STM32MP_NAND_TEED_OFFSET U(0x00680000) 165 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) 166 #endif 167 168 /******************************************************************************* 169 * STM32MP1 device/io map related constants (used for MMU) 170 ******************************************************************************/ 171 #define STM32MP1_DEVICE1_BASE U(0x40000000) 172 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 173 174 #define STM32MP1_DEVICE2_BASE U(0x80000000) 175 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 176 177 /******************************************************************************* 178 * STM32MP1 RCC 179 ******************************************************************************/ 180 #define RCC_BASE U(0x50000000) 181 182 /******************************************************************************* 183 * STM32MP1 PWR 184 ******************************************************************************/ 185 #define PWR_BASE U(0x50001000) 186 187 /******************************************************************************* 188 * STM32MP1 GPIO 189 ******************************************************************************/ 190 #define GPIOA_BASE U(0x50002000) 191 #define GPIOB_BASE U(0x50003000) 192 #define GPIOC_BASE U(0x50004000) 193 #define GPIOD_BASE U(0x50005000) 194 #define GPIOE_BASE U(0x50006000) 195 #define GPIOF_BASE U(0x50007000) 196 #define GPIOG_BASE U(0x50008000) 197 #define GPIOH_BASE U(0x50009000) 198 #define GPIOI_BASE U(0x5000A000) 199 #define GPIOJ_BASE U(0x5000B000) 200 #define GPIOK_BASE U(0x5000C000) 201 #define GPIOZ_BASE U(0x54004000) 202 #define GPIO_BANK_OFFSET U(0x1000) 203 204 /* Bank IDs used in GPIO driver API */ 205 #define GPIO_BANK_A U(0) 206 #define GPIO_BANK_B U(1) 207 #define GPIO_BANK_C U(2) 208 #define GPIO_BANK_D U(3) 209 #define GPIO_BANK_E U(4) 210 #define GPIO_BANK_F U(5) 211 #define GPIO_BANK_G U(6) 212 #define GPIO_BANK_H U(7) 213 #define GPIO_BANK_I U(8) 214 #define GPIO_BANK_J U(9) 215 #define GPIO_BANK_K U(10) 216 #define GPIO_BANK_Z U(25) 217 218 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 219 220 /******************************************************************************* 221 * STM32MP1 UART 222 ******************************************************************************/ 223 #define USART1_BASE U(0x5C000000) 224 #define USART2_BASE U(0x4000E000) 225 #define USART3_BASE U(0x4000F000) 226 #define UART4_BASE U(0x40010000) 227 #define UART5_BASE U(0x40011000) 228 #define USART6_BASE U(0x44003000) 229 #define UART7_BASE U(0x40018000) 230 #define UART8_BASE U(0x40019000) 231 #define STM32MP_UART_BAUDRATE U(115200) 232 233 /* For UART crash console */ 234 #define STM32MP_DEBUG_USART_BASE UART4_BASE 235 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 236 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 237 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 238 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 239 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 240 #define DEBUG_UART_TX_GPIO_PORT 11 241 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 242 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 243 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 244 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 245 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 246 247 /******************************************************************************* 248 * STM32MP1 TZC (TZ400) 249 ******************************************************************************/ 250 #define STM32MP1_TZC_BASE U(0x5C006000) 251 252 #define STM32MP1_TZC_A7_ID U(0) 253 #define STM32MP1_TZC_M4_ID U(1) 254 #define STM32MP1_TZC_LCD_ID U(3) 255 #define STM32MP1_TZC_GPU_ID U(4) 256 #define STM32MP1_TZC_MDMA_ID U(5) 257 #define STM32MP1_TZC_DMA_ID U(6) 258 #define STM32MP1_TZC_USB_HOST_ID U(7) 259 #define STM32MP1_TZC_USB_OTG_ID U(8) 260 #define STM32MP1_TZC_SDMMC_ID U(9) 261 #define STM32MP1_TZC_ETH_ID U(10) 262 #define STM32MP1_TZC_DAP_ID U(15) 263 264 #define STM32MP1_FILTER_BIT_ALL U(3) 265 266 /******************************************************************************* 267 * STM32MP1 SDMMC 268 ******************************************************************************/ 269 #define STM32MP_SDMMC1_BASE U(0x58005000) 270 #define STM32MP_SDMMC2_BASE U(0x58007000) 271 #define STM32MP_SDMMC3_BASE U(0x48004000) 272 273 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 274 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 275 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 276 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 277 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 278 279 /******************************************************************************* 280 * STM32MP1 BSEC / OTP 281 ******************************************************************************/ 282 #define STM32MP1_OTP_MAX_ID 0x5FU 283 #define STM32MP1_UPPER_OTP_START 0x20U 284 285 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 286 287 /* OTP offsets */ 288 #define DATA0_OTP U(0) 289 #define PART_NUMBER_OTP U(1) 290 #define NAND_OTP U(9) 291 #define PACKAGE_OTP U(16) 292 #define HW2_OTP U(18) 293 294 /* OTP mask */ 295 /* DATA0 */ 296 #define DATA0_OTP_SECURED BIT(6) 297 298 /* PART NUMBER */ 299 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 300 #define PART_NUMBER_OTP_PART_SHIFT 0 301 302 /* PACKAGE */ 303 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 304 #define PACKAGE_OTP_PKG_SHIFT 27 305 306 /* IWDG OTP */ 307 #define HW2_OTP_IWDG_HW_POS U(3) 308 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 309 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 310 311 /* HW2 OTP */ 312 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 313 314 /* NAND OTP */ 315 /* NAND parameter storage flag */ 316 #define NAND_PARAM_STORED_IN_OTP BIT(31) 317 318 /* NAND page size in bytes */ 319 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 320 #define NAND_PAGE_SIZE_SHIFT 29 321 #define NAND_PAGE_SIZE_2K U(0) 322 #define NAND_PAGE_SIZE_4K U(1) 323 #define NAND_PAGE_SIZE_8K U(2) 324 325 /* NAND block size in pages */ 326 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 327 #define NAND_BLOCK_SIZE_SHIFT 27 328 #define NAND_BLOCK_SIZE_64_PAGES U(0) 329 #define NAND_BLOCK_SIZE_128_PAGES U(1) 330 #define NAND_BLOCK_SIZE_256_PAGES U(2) 331 332 /* NAND number of block (in unit of 256 blocs) */ 333 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 334 #define NAND_BLOCK_NB_SHIFT 19 335 #define NAND_BLOCK_NB_UNIT U(256) 336 337 /* NAND bus width in bits */ 338 #define NAND_WIDTH_MASK BIT(18) 339 #define NAND_WIDTH_SHIFT 18 340 341 /* NAND number of ECC bits per 512 bytes */ 342 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 343 #define NAND_ECC_BIT_NB_SHIFT 15 344 #define NAND_ECC_BIT_NB_UNSET U(0) 345 #define NAND_ECC_BIT_NB_1_BITS U(1) 346 #define NAND_ECC_BIT_NB_4_BITS U(2) 347 #define NAND_ECC_BIT_NB_8_BITS U(3) 348 #define NAND_ECC_ON_DIE U(4) 349 350 /* NAND number of planes */ 351 #define NAND_PLANE_BIT_NB_MASK BIT(14) 352 353 /******************************************************************************* 354 * STM32MP1 TAMP 355 ******************************************************************************/ 356 #define TAMP_BASE U(0x5C00A000) 357 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 358 359 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 360 static inline uint32_t tamp_bkpr(uint32_t idx) 361 { 362 return TAMP_BKP_REGISTER_BASE + (idx << 2); 363 } 364 #endif 365 366 /******************************************************************************* 367 * STM32MP1 DDRCTRL 368 ******************************************************************************/ 369 #define DDRCTRL_BASE U(0x5A003000) 370 371 /******************************************************************************* 372 * STM32MP1 DDRPHYC 373 ******************************************************************************/ 374 #define DDRPHYC_BASE U(0x5A004000) 375 376 /******************************************************************************* 377 * STM32MP1 IWDG 378 ******************************************************************************/ 379 #define IWDG_MAX_INSTANCE U(2) 380 #define IWDG1_INST U(0) 381 #define IWDG2_INST U(1) 382 383 #define IWDG1_BASE U(0x5C003000) 384 #define IWDG2_BASE U(0x5A002000) 385 386 /******************************************************************************* 387 * STM32MP1 I2C4 388 ******************************************************************************/ 389 #define I2C4_BASE U(0x5C002000) 390 391 /******************************************************************************* 392 * STM32MP1 DBGMCU 393 ******************************************************************************/ 394 #define DBGMCU_BASE U(0x50081000) 395 396 /******************************************************************************* 397 * Device Tree defines 398 ******************************************************************************/ 399 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 400 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 401 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 402 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 403 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 404 405 #endif /* STM32MP1_DEF_H */ 406