1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/bl_common.h> 10 #include <drivers/arm/pl061_gpio.h> 11 #include <lib/gpt_rme/gpt_rme.h> 12 #include <lib/transfer_list.h> 13 #include <plat/common/platform.h> 14 #if ENABLE_RME 15 #include <qemu_pas_def.h> 16 #endif 17 #ifdef PLAT_qemu_sbsa 18 #include <sbsa_platform.h> 19 #endif 20 21 #include "qemu_private.h" 22 23 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 24 BL31_BASE, \ 25 BL31_END - BL31_BASE, \ 26 MT_MEMORY | MT_RW | EL3_PAS) 27 #define MAP_BL31_RO MAP_REGION_FLAT( \ 28 BL_CODE_BASE, \ 29 BL_CODE_END - BL_CODE_BASE, \ 30 MT_CODE | EL3_PAS), \ 31 MAP_REGION_FLAT( \ 32 BL_RO_DATA_BASE, \ 33 BL_RO_DATA_END \ 34 - BL_RO_DATA_BASE, \ 35 MT_RO_DATA | EL3_PAS) 36 37 #if USE_COHERENT_MEM 38 #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 39 BL_COHERENT_RAM_BASE, \ 40 BL_COHERENT_RAM_END \ 41 - BL_COHERENT_RAM_BASE, \ 42 MT_DEVICE | MT_RW | EL3_PAS) 43 #endif 44 45 /* 46 * Placeholder variables for copying the arguments that have been passed to 47 * BL3-1 from BL2. 48 */ 49 static entry_point_info_t bl32_image_ep_info; 50 static entry_point_info_t bl33_image_ep_info; 51 #if ENABLE_RME 52 static entry_point_info_t rmm_image_ep_info; 53 #endif 54 static struct transfer_list_header *bl31_tl; 55 56 /******************************************************************************* 57 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 58 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before 59 * they are lost (potentially). This needs to be done before the MMU is 60 * initialized so that the memory layout can be used while creating page 61 * tables. BL2 has flushed this information to memory, so we are guaranteed 62 * to pick up good data. 63 ******************************************************************************/ 64 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 65 u_register_t arg2, u_register_t arg3) 66 { 67 /* Initialize the console to provide early debug support */ 68 qemu_console_init(); 69 70 /* Platform names have to be lowercase. */ 71 #ifdef PLAT_qemu_sbsa 72 sbsa_platform_init(); 73 #endif 74 75 /* 76 * Check params passed from BL2 77 */ 78 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 79 80 assert(params_from_bl2); 81 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 82 assert(params_from_bl2->h.version >= VERSION_2); 83 84 bl_params_node_t *bl_params = params_from_bl2->head; 85 86 /* 87 * Copy BL33, BL32 and RMM (if present), entry point information. 88 * They are stored in Secure RAM, in BL2's address space. 89 */ 90 while (bl_params) { 91 if (bl_params->image_id == BL32_IMAGE_ID) 92 bl32_image_ep_info = *bl_params->ep_info; 93 94 #if ENABLE_RME 95 if (bl_params->image_id == RMM_IMAGE_ID) 96 rmm_image_ep_info = *bl_params->ep_info; 97 #endif 98 99 if (bl_params->image_id == BL33_IMAGE_ID) 100 bl33_image_ep_info = *bl_params->ep_info; 101 102 bl_params = bl_params->next_params_info; 103 } 104 105 if (!bl33_image_ep_info.pc) 106 panic(); 107 #if ENABLE_RME 108 if (!rmm_image_ep_info.pc) 109 panic(); 110 #endif 111 112 if (TRANSFER_LIST && arg1 == (TRANSFER_LIST_SIGNATURE | 113 REGISTER_CONVENTION_VERSION_MASK) && 114 transfer_list_check_header((void *)arg3) != TL_OPS_NON) { 115 bl31_tl = (void *)arg3; /* saved TL address from BL2 */ 116 } 117 } 118 119 #if ENABLE_RME 120 static void bl31_plat_gpt_setup(void) 121 { 122 /* 123 * The GPT library might modify the gpt regions structure to optimize 124 * the layout, so the array cannot be constant. 125 */ 126 pas_region_t pas_regions[] = { 127 QEMU_PAS_ROOT, 128 QEMU_PAS_SECURE, 129 QEMU_PAS_GPTS, 130 QEMU_PAS_NS0, 131 QEMU_PAS_REALM, 132 QEMU_PAS_NS1, 133 }; 134 135 /* 136 * Initialize entire protected space to GPT_GPI_ANY. With each L0 entry 137 * covering 1GB (currently the only supported option), then covering 138 * 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the 139 * moment we use a 8KB table, which covers 1TB of RAM (40-bit PA). 140 */ 141 if (gpt_init_l0_tables(PLATFORM_GPCCR_PPS, PLAT_QEMU_L0_GPT_BASE, 142 PLAT_QEMU_L0_GPT_SIZE + 143 PLAT_QEMU_GPT_BITLOCK_SIZE) < 0) { 144 ERROR("gpt_init_l0_tables() failed!\n"); 145 panic(); 146 } 147 148 /* Carve out defined PAS ranges. */ 149 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K, 150 PLAT_QEMU_L1_GPT_BASE, 151 PLAT_QEMU_L1_GPT_SIZE, 152 pas_regions, 153 (unsigned int)(sizeof(pas_regions) / 154 sizeof(pas_region_t))) < 0) { 155 ERROR("gpt_init_pas_l1_tables() failed!\n"); 156 panic(); 157 } 158 159 INFO("Enabling Granule Protection Checks\n"); 160 if (gpt_enable() < 0) { 161 ERROR("gpt_enable() failed!\n"); 162 panic(); 163 } 164 } 165 #endif 166 167 void bl31_plat_arch_setup(void) 168 { 169 const mmap_region_t bl_regions[] = { 170 MAP_BL31_TOTAL, 171 MAP_BL31_RO, 172 #if USE_COHERENT_MEM 173 MAP_BL_COHERENT_RAM, 174 #endif 175 #if ENABLE_RME 176 MAP_GPT_L0_REGION, 177 MAP_GPT_L1_REGION, 178 MAP_RMM_SHARED_MEM, 179 #endif 180 {0} 181 }; 182 183 setup_page_tables(bl_regions, plat_qemu_get_mmap()); 184 185 enable_mmu_el3(0); 186 187 #if ENABLE_RME 188 /* Initialise and enable granule protection after MMU. */ 189 bl31_plat_gpt_setup(); 190 191 /* 192 * Initialise Granule Protection library and enable GPC for the primary 193 * processor. The tables have already been initialized by a previous BL 194 * stage, so there is no need to provide any PAS here. This function 195 * sets up pointers to those tables. 196 */ 197 if (gpt_runtime_init() < 0) { 198 ERROR("gpt_runtime_init() failed!\n"); 199 panic(); 200 } 201 #endif /* ENABLE_RME */ 202 203 } 204 205 static void qemu_gpio_init(void) 206 { 207 #ifdef SECURE_GPIO_BASE 208 pl061_gpio_init(); 209 pl061_gpio_register(SECURE_GPIO_BASE, 0); 210 #endif 211 } 212 213 void bl31_platform_setup(void) 214 { 215 plat_qemu_gic_init(); 216 qemu_gpio_init(); 217 } 218 219 unsigned int plat_get_syscnt_freq2(void) 220 { 221 return read_cntfrq_el0(); 222 } 223 224 /******************************************************************************* 225 * Return a pointer to the 'entry_point_info' structure of the next image 226 * for the security state specified. BL3-3 corresponds to the non-secure 227 * image type while BL3-2 corresponds to the secure image type. A NULL 228 * pointer is returned if the image does not exist. 229 ******************************************************************************/ 230 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 231 { 232 entry_point_info_t *next_image_info; 233 234 assert(sec_state_is_valid(type)); 235 if (type == NON_SECURE) { 236 next_image_info = &bl33_image_ep_info; 237 } 238 #if ENABLE_RME 239 else if (type == REALM) { 240 next_image_info = &rmm_image_ep_info; 241 } 242 #endif 243 else { 244 next_image_info = &bl32_image_ep_info; 245 } 246 247 /* 248 * None of the images on the ARM development platforms can have 0x0 249 * as the entrypoint 250 */ 251 if (next_image_info->pc) 252 return next_image_info; 253 else 254 return NULL; 255 } 256 257 void bl31_plat_runtime_setup(void) 258 { 259 #if TRANSFER_LIST 260 if (bl31_tl) { 261 /* 262 * update the TL from S to NS memory before jump to BL33 263 * to reflect all changes in TL done by BL32 264 */ 265 memcpy((void *)FW_NS_HANDOFF_BASE, bl31_tl, bl31_tl->max_size); 266 } 267 #endif 268 269 console_flush(); 270 console_switch_state(CONSOLE_FLAG_RUNTIME); 271 } 272