| 837df485 | 24-Oct-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: remove unused tegra_mc_defs header
This patch removes the unused header from the Tegra194
platform files. As a result, the TSA MMIO would be
removed from the memory map too.
Change-Id: I2
Tegra194: remove unused tegra_mc_defs header
This patch removes the unused header from the Tegra194
platform files. As a result, the TSA MMIO would be
removed from the memory map too.
Change-Id: I2d38b3da7a119f5dfd6cfd429e481f4e6ad3481e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 08e60f80 | 26-Aug-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl: platform setup handler functions
The driver initially contained the setup steps to help Tegra186
and Tegra194 SoCs. In order to support future SoCs and make sure
that the driver rema
Tegra: memctrl: platform setup handler functions
The driver initially contained the setup steps to help Tegra186
and Tegra194 SoCs. In order to support future SoCs and make sure
that the driver remains generic enough, some code should be moved
to SoC.
This patch creates a setup handler for a platform to implement its
initialization sequence.
Change-Id: I8bab7fd07f25e0457ead8e2d2713efe54782a59b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 872a1c52 | 11-Apr-2019 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: memctrl: remove streamid security cfg registers
The stream ID security configuration settings shall be done by the
previous level bootloader. This change removes the same settings
from the
Tegra194: memctrl: remove streamid security cfg registers
The stream ID security configuration settings shall be done by the
previous level bootloader. This change removes the same settings
from the Tegra194 platform code as a result.
Change-Id: Ia170ca4c2119db8f1d0251f1c193add006f81004
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
show more ...
|
| bdd61c16 | 28-Apr-2019 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: memctrl: remove streamid override cfg registers
The stream ID override configuration is saved during System Suspend
as part MB1 bct. This change removes the same support from the Tegra194
Tegra194: memctrl: remove streamid override cfg registers
The stream ID override configuration is saved during System Suspend
as part MB1 bct. This change removes the same support from the Tegra194
platform code as a result.
Change-Id: I4c19dc0d8b29190908673fb5ed7ed892af8906ab
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
show more ...
|
| 5ce05d6b | 05-Feb-2020 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra194: add strict checking mode verification
After enabling the strict checking mode, verify that
the strict mode has really been enabled by querying
the MCE.
If the mode is found to be disabled
Tegra194: add strict checking mode verification
After enabling the strict checking mode, verify that
the strict mode has really been enabled by querying
the MCE.
If the mode is found to be disabled, the code should
assert.
Change-Id: I113ec8decb737f8208059a2a3ba3076fad77890e
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
show more ...
|
| 7e491133 | 22-Apr-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: memctrl: update TZDRAM base at 1MB granularity
The Memory controller expects the TZDRAM base value at 1MB granularity
and the current driver does not respect that limitation. This patch
fi
Tegra194: memctrl: update TZDRAM base at 1MB granularity
The Memory controller expects the TZDRAM base value at 1MB granularity
and the current driver does not respect that limitation. This patch
fixes that anomaly.
Change-Id: I6b72270f331ba5081e19811df4a78623e457341a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| ebd720d0 | 07-Jun-2019 |
David Pu <dpu@nvidia.com> |
Tegra194: ras: split up RAS error clear SMC call.
In order to make sure SMC call is within 25us, this patch reduces number of RAS
errors accessed to 8 at most for each SMC call and takes a input/out
Tegra194: ras: split up RAS error clear SMC call.
In order to make sure SMC call is within 25us, this patch reduces number of RAS
errors accessed to 8 at most for each SMC call and takes a input/output
parameter to specify in progress RAS error record index.
The measured SMC call latency is about 20us under Linux test kernel driver.
Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f
Signed-off-by: David Pu <dpu@nvidia.com>
show more ...
|
| 7581dc89 | 26-Feb-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: platform specific GIC sources
The TEGRA_GICv2_SOURCES contains the list of GIC sources required
to compile the GICv2 support for platforms.
This patch includes the TEGRA_GICv2_SOURCES macro
Tegra: platform specific GIC sources
The TEGRA_GICv2_SOURCES contains the list of GIC sources required
to compile the GICv2 support for platforms.
This patch includes the TEGRA_GICv2_SOURCES macro from individual
makefiles to allow future platforms to use suport for GICv3.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I429b1a0c7764ab370675f873a50cecda871110cb
show more ...
|
| 1740ed12 | 15-Nov-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: add memory barriers during DRAM to SysRAM copy
This patch adds memory barriers to the trampoline code copying TZDRAM
contents to SysRAM during exit from System Suspend. These barriers
make
Tegra194: add memory barriers during DRAM to SysRAM copy
This patch adds memory barriers to the trampoline code copying TZDRAM
contents to SysRAM during exit from System Suspend. These barriers
make sure that all the copies go through before we start executing in
SysRAM.
Reported by: Nathan Tuck <ntuck@nvidia.com>
Change-Id: I3fd2964086b6c0e044cc4165051a4801440db9cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 2561cb50 | 13-Nov-2019 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra194: add redundancy checks for MMIO writes
MMIO writes should verify that the writes actually went through.
Read the value back after the write operation, perform assert
if the read back value
Tegra194: add redundancy checks for MMIO writes
MMIO writes should verify that the writes actually went through.
Read the value back after the write operation, perform assert
if the read back value is not same as the write value.
Change-Id: Id2ceb014116f3aa6a9e86505ca1ae9911470a679
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
show more ...
|
| e26810aa | 07-Nov-2019 |
Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> |
Tegra194: report failure to enable dual execution
During boot the platform enables dual execution for Xavier CPUs.
This patch reads back the ACTLR_ELx register to verify that the bit
is actually set
Tegra194: report failure to enable dual execution
During boot the platform enables dual execution for Xavier CPUs.
This patch reads back the ACTLR_ELx register to verify that the bit
is actually set. It asserts if the bit is not set.
Change-Id: I5ba9491ced86285d307b95efa647a427ff77c79e
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
show more ...
|
| 22e4f948 | 02-Oct-2019 |
Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> |
Tegra194: verify firewall settings before resource use
The firewall settings for the hardware resources are present in the
Security Configuration Registers. The firewall settings are programmed
by o
Tegra194: verify firewall settings before resource use
The firewall settings for the hardware resources are present in the
Security Configuration Registers. The firewall settings are programmed
by other software components and so must be verified for correctness
before touching the hardware resources they protect.
This patch reads the firewall settings during early boot and asserts
if the settings mismatch.
Change-Id: I53cc9aeadad32e54e460db0fa2c38e46bcc92066
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 3e1e08b7 | 25-Aug-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "tegra194-spmd" into integration
* changes:
Tegra194: introduce support for `SPD=spmd`
Tegra: introduce backend support to compile libfdt
Tegra: disable signed compari
Merge changes from topic "tegra194-spmd" into integration
* changes:
Tegra194: introduce support for `SPD=spmd`
Tegra: introduce backend support to compile libfdt
Tegra: disable signed comparison
plat: common: include "bl_common.h" from plat_spmd_manifest.c
show more ...
|
| 670306d3 | 20-Jul-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: introduce support for `SPD=spmd`
This patch introduces the following changes to enable
compilation for `SPD=spmd` command line option.
* compile plat_spmd_manifest.c
* compile libfdt sour
Tegra194: introduce support for `SPD=spmd`
This patch introduces the following changes to enable
compilation for `SPD=spmd` command line option.
* compile plat_spmd_manifest.c
* compile libfdt source files
Verified with the `SPD=spmd` command line option for
Tegra194 platforms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I7f57aa4f1756b19f78d87415bb80794417174bc8
show more ...
|
| be41aac7 | 17-Feb-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: remove AON_WDT IRQ mapping
This patch removes the unused interrupt mapping for AON_WDT
for all Tegra194 platforms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I475a1e83f
Tegra194: remove AON_WDT IRQ mapping
This patch removes the unused interrupt mapping for AON_WDT
for all Tegra194 platforms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I475a1e83f809c740e62464b5b4e93cb0a2e33d6b
show more ...
|
| 13fed5a7 | 22-Aug-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: TZDRAM setup from soc specific early_boot handlers
TZDRAM setup is not required for all Tegra SoCs. The previous bootloader
can enable the TZDRAM fence due to architectural improvements in th
Tegra: TZDRAM setup from soc specific early_boot handlers
TZDRAM setup is not required for all Tegra SoCs. The previous bootloader
can enable the TZDRAM fence due to architectural improvements in the
newer chips.
This patch moves the TZDRAM setup to early_boot handlers for SoCs to
handle this scenario.
Change-Id: I6481b4f848a4dadc20cb83852cd8e19a242b3a34
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| fbcd053c | 13-Sep-2019 |
kalyanic <kalyanic@nvidia.com> |
Tegra: verify platform compatibility
This patch verifies that the binary image is compatible with
chip ID of the platform.
Change-Id: I28db221b4442aa8827a092faadf32f110d7c5cb4
Signed-off-by: kalyan
Tegra: verify platform compatibility
This patch verifies that the binary image is compatible with
chip ID of the platform.
Change-Id: I28db221b4442aa8827a092faadf32f110d7c5cb4
Signed-off-by: kalyanic <kalyanic@nvidia.com>
show more ...
|
| e2469d82 | 13-Jun-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: reorganize drivers and lib folders
This patch moves the 'drivers' and the 'lib' folders out of the
'common' folder. This way the 'common' folder shall contain only
the platform support requir
Tegra: reorganize drivers and lib folders
This patch moves the 'drivers' and the 'lib' folders out of the
'common' folder. This way the 'common' folder shall contain only
the platform support required for all Tegra platforms.
Change-Id: I2f238572d0a078d60c6b458a559538dc8a4d1856
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| fba5cdc6 | 17-May-2019 |
David Pu <dpu@nvidia.com> |
Tegra194: ras: verbose prints for SErrors
This patch provides verbose prints for RAS SErrors handled by the
firmware, for improved debugging.
Change-Id: Iaad8d183054d884f606dc4621da2cc6b2375bcf9
Si
Tegra194: ras: verbose prints for SErrors
This patch provides verbose prints for RAS SErrors handled by the
firmware, for improved debugging.
Change-Id: Iaad8d183054d884f606dc4621da2cc6b2375bcf9
Signed-off-by: David Pu <dpu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 0d851195 | 21-Mar-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: SiP: clear RAS corrected error records
This patch introduces a function ID to clear all the RAS error
records for corrected errors.
Per latest requirement, ARM RAS corrected errors will b
Tegra194: SiP: clear RAS corrected error records
This patch introduces a function ID to clear all the RAS error
records for corrected errors.
Per latest requirement, ARM RAS corrected errors will be reported to
lower ELs via interrupts and cleared via SMC. This patch provides
required function to clear RAS error status.
This patch also sets up all required RAS Corrected errors in order to
route RAS corrected errors to lower ELs.
Change-Id: I554ba1d0797b736835aa27824782703682c91e51
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: David Pu <dpu@nvidia.com>
show more ...
|
| 8ca61538 | 18-Mar-2019 |
David Pu <dpu@nvidia.com> |
Tegra194: add RAS exception handling
This patch adds all Tegra194 RAS nodes definitions and support to
handle all uncorrectable RAS errors.
Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9
Sign
Tegra194: add RAS exception handling
This patch adds all Tegra194 RAS nodes definitions and support to
handle all uncorrectable RAS errors.
Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9
Signed-off-by: David Pu <dpu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| de9d0d7c | 21-May-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Tegra: enable SDEI handling" into integration |
| d886628d | 18-Apr-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: enable SDEI handling
This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.
* SGI 8 as the source IRQ
* Special Private Event 0
* Three private,
Tegra: enable SDEI handling
This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.
* SGI 8 as the source IRQ
* Special Private Event 0
* Three private, dynamic events
* Three shared, dynamic events
* Twelve general purpose explicit events
Verified using TFTF SDEI test suite.
******************************* Summary *******************************
Test suite 'SDEI' Passed
=================================
Tests Skipped : 0
Tests Passed : 5
Tests Failed : 0
Tests Crashed : 0
Total tests : 5
=================================
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390
show more ...
|
| bc693ecc | 06-May-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: validate C6 power state type
This patch validates that PSTATE_STANDBY is set as the C6 power state type.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I26a4a61bcb4ee0d1846
Tegra194: validate C6 power state type
This patch validates that PSTATE_STANDBY is set as the C6 power state type.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I26a4a61bcb4ee0d1846ab61c007eeba3c180e5aa
show more ...
|
| e3e5e661 | 23-Apr-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: remove support for CPU suspend power down state
Tegra194 platforms removed support to power down CPUs during CPU suspend. This
patch removes the support for CPU suspend power down as a res
Tegra194: remove support for CPU suspend power down state
Tegra194 platforms removed support to power down CPUs during CPU suspend. This
patch removes the support for CPU suspend power down as a result.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifde72c90c194582a79fb80904154b9886413f16e
show more ...
|