1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <arch_helpers.h> 13 #include <bpmp_ipc.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <context.h> 17 #include <drivers/delay_timer.h> 18 #include <denver.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/psci/psci.h> 21 #include <mce.h> 22 #include <mce_private.h> 23 #include <memctrl_v2.h> 24 #include <plat/common/platform.h> 25 #include <se.h> 26 #include <smmu.h> 27 #include <t194_nvg.h> 28 #include <tegra194_private.h> 29 #include <tegra_platform.h> 30 #include <tegra_private.h> 31 32 extern uint32_t __tegra194_cpu_reset_handler_data, 33 __tegra194_cpu_reset_handler_end; 34 35 /* TZDRAM offset for saving SMMU context */ 36 #define TEGRA194_SMMU_CTX_OFFSET 16U 37 38 /* state id mask */ 39 #define TEGRA194_STATE_ID_MASK 0xFU 40 /* constants to get power state's wake time */ 41 #define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U 42 #define TEGRA194_WAKE_TIME_SHIFT 4U 43 /* default core wake mask for CPU_SUSPEND */ 44 #define TEGRA194_CORE_WAKE_MASK 0x180cU 45 46 static struct t19x_psci_percpu_data { 47 uint32_t wake_time; 48 } __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT]; 49 50 int32_t tegra_soc_validate_power_state(uint32_t power_state, 51 psci_power_state_t *req_state) 52 { 53 uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & 54 TEGRA194_STATE_ID_MASK; 55 uint32_t cpu = plat_my_core_pos(); 56 int32_t ret = PSCI_E_SUCCESS; 57 58 /* save the core wake time (in TSC ticks)*/ 59 t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK) 60 << TEGRA194_WAKE_TIME_SHIFT; 61 62 /* 63 * Clean t19x_percpu_data[cpu] to DRAM. This needs to be done to ensure 64 * that the correct value is read in tegra_soc_pwr_domain_suspend(), 65 * which is called with caches disabled. It is possible to read a stale 66 * value from DRAM in that function, because the L2 cache is not flushed 67 * unless the cluster is entering CC6/CC7. 68 */ 69 clean_dcache_range((uint64_t)&t19x_percpu_data[cpu], 70 sizeof(t19x_percpu_data[cpu])); 71 72 /* Sanity check the requested state id */ 73 switch (state_id) { 74 case PSTATE_ID_CORE_IDLE: 75 76 /* Core idle request */ 77 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 78 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN; 79 break; 80 81 default: 82 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 83 ret = PSCI_E_INVALID_PARAMS; 84 break; 85 } 86 87 return ret; 88 } 89 90 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state) 91 { 92 uint32_t cpu = plat_my_core_pos(); 93 mce_cstate_info_t cstate_info = { 0 }; 94 95 /* Program default wake mask */ 96 cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; 97 cstate_info.update_wake_mask = 1; 98 mce_update_cstate_info(&cstate_info); 99 100 /* Enter CPU idle */ 101 (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, 102 (uint64_t)TEGRA_NVG_CORE_C6, 103 t19x_percpu_data[cpu].wake_time, 104 0U); 105 106 return PSCI_E_SUCCESS; 107 } 108 109 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 110 { 111 const plat_local_state_t *pwr_domain_state; 112 uint8_t stateid_afflvl2; 113 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 114 uint64_t mc_ctx_base; 115 uint32_t val; 116 mce_cstate_info_t sc7_cstate_info = { 117 .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6, 118 .ccplex = (uint32_t)TEGRA_NVG_CG_CG7, 119 .system = (uint32_t)TEGRA_NVG_SYSTEM_SC7, 120 .system_state_force = 1U, 121 .update_wake_mask = 1U, 122 }; 123 int32_t ret = 0; 124 125 /* get the state ID */ 126 pwr_domain_state = target_state->pwr_domain_state; 127 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 128 TEGRA194_STATE_ID_MASK; 129 130 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 131 132 /* save 'Secure Boot' Processor Feature Config Register */ 133 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); 134 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); 135 136 /* save MC context */ 137 mc_ctx_base = params_from_bl2->tzdram_base + 138 tegra194_get_mc_ctx_offset(); 139 tegra_mc_save_context((uintptr_t)mc_ctx_base); 140 141 /* 142 * Suspend SE, RNG1 and PKA1 only on silcon and fpga, 143 * since VDK does not support atomic se ctx save 144 */ 145 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { 146 ret = tegra_se_suspend(); 147 assert(ret == 0); 148 } 149 150 /* Prepare for system suspend */ 151 mce_update_cstate_info(&sc7_cstate_info); 152 153 do { 154 val = (uint32_t)mce_command_handler( 155 (uint32_t)MCE_CMD_IS_SC7_ALLOWED, 156 (uint32_t)TEGRA_NVG_CORE_C7, 157 MCE_CORE_SLEEP_TIME_INFINITE, 158 0U); 159 } while (val == 0U); 160 161 /* Instruct the MCE to enter system suspend state */ 162 ret = mce_command_handler( 163 (uint64_t)MCE_CMD_ENTER_CSTATE, 164 (uint64_t)TEGRA_NVG_CORE_C7, 165 MCE_CORE_SLEEP_TIME_INFINITE, 166 0U); 167 assert(ret == 0); 168 169 /* set system suspend state for house-keeping */ 170 tegra194_set_system_suspend_entry(); 171 } 172 173 return PSCI_E_SUCCESS; 174 } 175 176 /******************************************************************************* 177 * Helper function to check if this is the last ON CPU in the cluster 178 ******************************************************************************/ 179 static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states, 180 uint32_t ncpu) 181 { 182 plat_local_state_t target; 183 bool last_on_cpu = true; 184 uint32_t num_cpus = ncpu, pos = 0; 185 186 do { 187 target = states[pos]; 188 if (target != PLAT_MAX_OFF_STATE) { 189 last_on_cpu = false; 190 } 191 --num_cpus; 192 pos++; 193 } while (num_cpus != 0U); 194 195 return last_on_cpu; 196 } 197 198 /******************************************************************************* 199 * Helper function to get target power state for the cluster 200 ******************************************************************************/ 201 static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, 202 uint32_t ncpu) 203 { 204 uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK; 205 plat_local_state_t target = states[core_pos]; 206 mce_cstate_info_t cstate_info = { 0 }; 207 208 /* CPU off */ 209 if (target == PLAT_MAX_OFF_STATE) { 210 211 /* Enable cluster powerdn from last CPU in the cluster */ 212 if (tegra_last_on_cpu_in_cluster(states, ncpu)) { 213 214 /* Enable CC6 state and turn off wake mask */ 215 cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6; 216 cstate_info.ccplex = (uint32_t)TEGRA_NVG_CG_CG7; 217 cstate_info.system_state_force = 1; 218 cstate_info.update_wake_mask = 1U; 219 mce_update_cstate_info(&cstate_info); 220 221 } else { 222 223 /* Turn off wake_mask */ 224 cstate_info.update_wake_mask = 1U; 225 mce_update_cstate_info(&cstate_info); 226 target = PSCI_LOCAL_STATE_RUN; 227 } 228 } 229 230 return target; 231 } 232 233 /******************************************************************************* 234 * Platform handler to calculate the proper target power level at the 235 * specified affinity level 236 ******************************************************************************/ 237 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 238 const plat_local_state_t *states, 239 uint32_t ncpu) 240 { 241 plat_local_state_t target = PSCI_LOCAL_STATE_RUN; 242 uint32_t cpu = plat_my_core_pos(); 243 244 /* System Suspend */ 245 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { 246 target = PSTATE_ID_SOC_POWERDN; 247 } 248 249 /* CPU off, CPU suspend */ 250 if (lvl == (uint32_t)MPIDR_AFFLVL1) { 251 target = tegra_get_afflvl1_pwr_state(states, ncpu); 252 } 253 254 /* target cluster/system state */ 255 return target; 256 } 257 258 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 259 { 260 const plat_local_state_t *pwr_domain_state = 261 target_state->pwr_domain_state; 262 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 263 uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 264 TEGRA194_STATE_ID_MASK; 265 uint64_t src_len_in_bytes = (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE; 266 uint64_t val; 267 int32_t ret = PSCI_E_SUCCESS; 268 269 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 270 val = params_from_bl2->tzdram_base + 271 tegra194_get_cpu_reset_handler_size(); 272 273 /* initialise communication channel with BPMP */ 274 ret = tegra_bpmp_ipc_init(); 275 assert(ret == 0); 276 277 /* Enable SE clock before SE context save */ 278 ret = tegra_bpmp_ipc_enable_clock(TEGRA194_CLK_SE); 279 assert(ret == 0); 280 281 /* 282 * It is very unlikely that the BL31 image would be 283 * bigger than 2^32 bytes 284 */ 285 assert(src_len_in_bytes < UINT32_MAX); 286 287 if (tegra_se_calculate_save_sha256(BL31_BASE, 288 (uint32_t)src_len_in_bytes) != 0) { 289 ERROR("Hash calculation failed. Reboot\n"); 290 (void)tegra_soc_prepare_system_reset(); 291 } 292 293 /* 294 * The TZRAM loses power when we enter system suspend. To 295 * allow graceful exit from system suspend, we need to copy 296 * BL3-1 over to TZDRAM. 297 */ 298 val = params_from_bl2->tzdram_base + 299 tegra194_get_cpu_reset_handler_size(); 300 memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, 301 src_len_in_bytes); 302 303 /* Disable SE clock after SE context save */ 304 ret = tegra_bpmp_ipc_disable_clock(TEGRA194_CLK_SE); 305 assert(ret == 0); 306 } 307 308 return ret; 309 } 310 311 int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) 312 { 313 return PSCI_E_NOT_SUPPORTED; 314 } 315 316 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) 317 { 318 uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; 319 uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 320 MPIDR_AFFINITY_BITS; 321 int32_t ret = 0; 322 323 if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) { 324 ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr); 325 return PSCI_E_NOT_PRESENT; 326 } 327 328 /* construct the target CPU # */ 329 target_cpu += (target_cluster << 1U); 330 331 ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); 332 if (ret < 0) { 333 return PSCI_E_DENIED; 334 } 335 336 return PSCI_E_SUCCESS; 337 } 338 339 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 340 { 341 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 342 uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step; 343 uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; 344 cpu_context_t *ctx = cm_get_context(NON_SECURE); 345 uint64_t actlr_elx; 346 347 /* 348 * Reset power state info for CPUs when onlining, we set 349 * deepest power when offlining a core but that may not be 350 * requested by non-secure sw which controls idle states. It 351 * will re-init this info from non-secure software when the 352 * core come online. 353 */ 354 actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1)); 355 actlr_elx &= ~DENVER_CPU_PMSTATE_MASK; 356 actlr_elx |= DENVER_CPU_PMSTATE_C1; 357 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 358 359 /* 360 * Check if we are exiting from deep sleep and restore SE 361 * context if we are. 362 */ 363 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 364 365 #if ENABLE_STRICT_CHECKING_MODE 366 /* 367 * Enable strict checking after programming the GSC for 368 * enabling TZSRAM and TZDRAM 369 */ 370 mce_enable_strict_checking(); 371 #endif 372 373 /* Init SMMU */ 374 tegra_smmu_init(); 375 376 /* Resume SE, RNG1 and PKA1 */ 377 tegra_se_resume(); 378 379 /* 380 * Program XUSB STREAMIDs 381 * ====================== 382 * T19x XUSB has support for XUSB virtualization. It will 383 * have one physical function (PF) and four Virtual functions 384 * (VF) 385 * 386 * There were below two SIDs for XUSB until T186. 387 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 388 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 389 * 390 * We have below four new SIDs added for VF(s) 391 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 392 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 393 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 394 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 395 * 396 * When virtualization is enabled then we have to disable SID 397 * override and program above SIDs in below newly added SID 398 * registers in XUSB PADCTL MMIO space. These registers are 399 * TZ protected and so need to be done in ATF. 400 * 401 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 402 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 403 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 404 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 405 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 406 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 407 * 408 * This change disables SID override and programs XUSB SIDs 409 * in above registers to support both virtualization and 410 * non-virtualization platforms 411 */ 412 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { 413 414 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 415 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 416 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 417 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 418 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 419 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 420 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 421 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 422 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 423 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 424 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 425 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 426 } 427 } 428 429 /* 430 * Enable dual execution optimized translations for all ELx. 431 */ 432 if (enable_ccplex_lock_step != 0U) { 433 actlr_elx = read_actlr_el3(); 434 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3; 435 write_actlr_el3(actlr_elx); 436 437 actlr_elx = read_actlr_el2(); 438 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2; 439 write_actlr_el2(actlr_elx); 440 441 actlr_elx = read_actlr_el1(); 442 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1; 443 write_actlr_el1(actlr_elx); 444 } 445 446 return PSCI_E_SUCCESS; 447 } 448 449 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 450 { 451 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 452 int32_t ret = 0; 453 454 (void)target_state; 455 456 /* Disable Denver's DCO operations */ 457 if (impl == DENVER_IMPL) { 458 denver_disable_dco(); 459 } 460 461 /* Turn off CPU */ 462 ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, 463 (uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); 464 assert(ret == 0); 465 466 return PSCI_E_SUCCESS; 467 } 468 469 __dead2 void tegra_soc_prepare_system_off(void) 470 { 471 /* System power off */ 472 mce_system_shutdown(); 473 474 wfi(); 475 476 /* wait for the system to power down */ 477 for (;;) { 478 ; 479 } 480 } 481 482 int32_t tegra_soc_prepare_system_reset(void) 483 { 484 /* System reboot */ 485 mce_system_reboot(); 486 487 return PSCI_E_SUCCESS; 488 } 489