1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/bl_common.h> 9 #include <mce.h> 10 #include <memctrl_v2.h> 11 #include <tegra_mc_def.h> 12 #include <tegra_platform.h> 13 14 /******************************************************************************* 15 * Array to hold the security configs for stream IDs 16 ******************************************************************************/ 17 const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { 18 mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE), 19 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE), 20 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 21 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 22 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE), 23 mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, DISABLE), 24 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 25 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE), 26 mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, DISABLE), 27 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE), 28 mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), 29 mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 30 mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), 31 mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), 32 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE), 33 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE), 34 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE), 35 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE), 36 mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 37 mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 38 mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE), 39 mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE), 40 mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE), 41 mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE), 42 mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE), 43 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE), 44 mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 45 mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 46 mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), 47 mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 48 mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 49 mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE), 50 mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE), 51 mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 52 mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 53 mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE), 54 mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE), 55 mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, DISABLE), 56 mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, DISABLE), 57 mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE), 58 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE), 59 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 60 mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 61 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), 62 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), 63 mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE), 64 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE), 65 mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE), 66 mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE), 67 mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE), 68 mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE), 69 mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE), 70 mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 71 mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 72 mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE), 73 mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE), 74 mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 75 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 76 mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE), 77 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE), 78 mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 79 mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 80 mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 81 mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 82 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE), 83 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 84 mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 85 mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 86 mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 87 mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 88 mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 89 mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 90 mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 91 mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 92 mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 93 mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 94 mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 95 mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 96 mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, DISABLE), 97 mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, DISABLE), 98 mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 99 mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, DISABLE), 100 mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, DISABLE), 101 mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 102 mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, DISABLE), 103 mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, DISABLE), 104 mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 105 mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, DISABLE), 106 mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, DISABLE), 107 mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, DISABLE), 108 mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, DISABLE), 109 mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 110 mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 111 mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE), 112 mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE), 113 mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, DISABLE), 114 mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, DISABLE), 115 mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, DISABLE), 116 mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, DISABLE), 117 mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, DISABLE), 118 mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, DISABLE), 119 mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, DISABLE), 120 mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, DISABLE), 121 mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, DISABLE), 122 mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, DISABLE), 123 mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, DISABLE), 124 mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, DISABLE), 125 mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 126 mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 127 mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 128 mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 129 mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, DISABLE), 130 mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 131 mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, DISABLE), 132 mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, DISABLE), 133 mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 134 mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 135 mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), 136 mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, DISABLE), 137 mc_make_sec_cfg(NVDEC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE), 138 mc_make_sec_cfg(NVDEC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 139 mc_make_sec_cfg(NVDEC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE), 140 mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, DISABLE), 141 mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, DISABLE), 142 mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, DISABLE), 143 mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, DISABLE), 144 mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, DISABLE), 145 mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, DISABLE), 146 mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, DISABLE), 147 mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE), 148 mc_make_sec_cfg(MIU4R, NON_SECURE, OVERRIDE, DISABLE), 149 mc_make_sec_cfg(MIU4W, NON_SECURE, OVERRIDE, DISABLE), 150 mc_make_sec_cfg(MIU5R, NON_SECURE, OVERRIDE, DISABLE), 151 mc_make_sec_cfg(MIU5W, NON_SECURE, OVERRIDE, DISABLE), 152 mc_make_sec_cfg(MIU6R, NON_SECURE, OVERRIDE, DISABLE), 153 mc_make_sec_cfg(MIU6W, NON_SECURE, OVERRIDE, DISABLE), 154 mc_make_sec_cfg(MIU7R, NON_SECURE, OVERRIDE, DISABLE), 155 mc_make_sec_cfg(MIU7W, NON_SECURE, OVERRIDE, DISABLE) 156 }; 157 158 /******************************************************************************* 159 * Array to hold MC context for Tegra194 160 ******************************************************************************/ 161 static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = { 162 _START_OF_TABLE_, 163 mc_smmu_bypass_cfg, /* TBU settings */ 164 _END_OF_TABLE_, 165 }; 166 167 /******************************************************************************* 168 * Handler to return the pointer to the MC's context struct 169 ******************************************************************************/ 170 static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void) 171 { 172 /* index of _END_OF_TABLE_ */ 173 tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U; 174 175 return tegra194_mc_context; 176 } 177 178 /******************************************************************************* 179 * Struct to hold the memory controller settings 180 ******************************************************************************/ 181 static tegra_mc_settings_t tegra194_mc_settings = { 182 .streamid_security_cfg = tegra194_streamid_sec_cfgs, 183 .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), 184 .get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx 185 }; 186 187 /******************************************************************************* 188 * Handler to return the pointer to the memory controller's settings struct 189 ******************************************************************************/ 190 tegra_mc_settings_t *tegra_get_mc_settings(void) 191 { 192 return &tegra194_mc_settings; 193 } 194 195 /******************************************************************************* 196 * Handler to program the scratch registers with TZDRAM settings for the 197 * resume firmware 198 ******************************************************************************/ 199 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 200 { 201 uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); 202 uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000; 203 uint32_t phys_base_hi = (uint32_t)(phys_base >> 32); 204 205 /* 206 * Check TZDRAM carveout register access status. Setup TZDRAM fence 207 * only if access is enabled. 208 */ 209 if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == 210 SECURITY_CFG_WRITE_ACCESS_ENABLE) { 211 212 /* 213 * Setup the Memory controller to allow only secure accesses to 214 * the TZDRAM carveout 215 */ 216 INFO("Configuring TrustZone DRAM Memory Carveout\n"); 217 218 tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo); 219 tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi); 220 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); 221 222 /* 223 * MCE propagates the security configuration values across the 224 * CCPLEX. 225 */ 226 (void)mce_update_gsc_tzdram(); 227 } 228 } 229