1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/bl_common.h> 9 #include <mce.h> 10 #include <memctrl_v2.h> 11 #include <tegra_mc_def.h> 12 #include <tegra_platform.h> 13 14 /******************************************************************************* 15 * Array to hold MC context for Tegra194 16 ******************************************************************************/ 17 static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = { 18 _START_OF_TABLE_, 19 mc_smmu_bypass_cfg, /* TBU settings */ 20 _END_OF_TABLE_, 21 }; 22 23 /******************************************************************************* 24 * Handler to return the pointer to the MC's context struct 25 ******************************************************************************/ 26 static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void) 27 { 28 /* index of _END_OF_TABLE_ */ 29 tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U; 30 31 return tegra194_mc_context; 32 } 33 34 /******************************************************************************* 35 * Struct to hold the memory controller settings 36 ******************************************************************************/ 37 static tegra_mc_settings_t tegra194_mc_settings = { 38 .get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx 39 }; 40 41 /******************************************************************************* 42 * Handler to return the pointer to the memory controller's settings struct 43 ******************************************************************************/ 44 tegra_mc_settings_t *tegra_get_mc_settings(void) 45 { 46 return &tegra194_mc_settings; 47 } 48 49 /******************************************************************************* 50 * Handler to program the scratch registers with TZDRAM settings for the 51 * resume firmware 52 ******************************************************************************/ 53 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 54 { 55 uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); 56 uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000; 57 uint32_t phys_base_hi = (uint32_t)(phys_base >> 32); 58 59 /* 60 * Check TZDRAM carveout register access status. Setup TZDRAM fence 61 * only if access is enabled. 62 */ 63 if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == 64 SECURITY_CFG_WRITE_ACCESS_ENABLE) { 65 66 /* 67 * Setup the Memory controller to allow only secure accesses to 68 * the TZDRAM carveout 69 */ 70 INFO("Configuring TrustZone DRAM Memory Carveout\n"); 71 72 tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo); 73 tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi); 74 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); 75 76 /* 77 * MCE propagates the security configuration values across the 78 * CCPLEX. 79 */ 80 (void)mce_update_gsc_tzdram(); 81 } 82 } 83