1 /* 2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/cadence/cdns_sdmmc.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/synopsys/dw_mmc.h> 18 #include <drivers/ti/uart/uart_16550.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 22 #include "agilex5_clock_manager.h" 23 #include "agilex5_ddr.h" 24 #include "agilex5_memory_controller.h" 25 #include "agilex5_mmc.h" 26 #include "agilex5_pinmux.h" 27 #include "agilex5_system_manager.h" 28 #include "ccu/ncore_ccu.h" 29 #include "combophy/combophy.h" 30 #include "nand/nand.h" 31 #include "qspi/cadence_qspi.h" 32 #include "sdmmc/sdmmc.h" 33 #include "socfpga_emac.h" 34 #include "socfpga_f2sdram_manager.h" 35 #include "socfpga_handoff.h" 36 #include "socfpga_mailbox.h" 37 #include "socfpga_private.h" 38 #include "socfpga_reset_manager.h" 39 #include "socfpga_ros.h" 40 #include "socfpga_vab.h" 41 #include "wdt/watchdog.h" 42 43 44 /* Declare mmc_info */ 45 static struct mmc_device_info mmc_info; 46 47 /* Declare cadence idmac descriptor */ 48 extern struct cdns_idmac_desc cdns_desc[8] __aligned(32); 49 50 const mmap_region_t agilex_plat_mmap[] = { 51 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 52 MT_MEMORY | MT_RW | MT_NS), 53 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, 54 MT_DEVICE | MT_RW | MT_NS), 55 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, 56 MT_DEVICE | MT_RW | MT_SECURE), 57 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 58 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 59 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, 60 MT_DEVICE | MT_RW | MT_SECURE), 61 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 62 MT_DEVICE | MT_RW | MT_NS), 63 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, 64 MT_DEVICE | MT_RW | MT_SECURE), 65 {0}, 66 }; 67 68 boot_source_type boot_source = BOOT_SOURCE; 69 70 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 71 u_register_t x2, u_register_t x4) 72 { 73 static console_t console; 74 75 handoff reverse_handoff_ptr = { 0 }; 76 77 generic_delay_timer_init(); 78 config_clkmgr_handoff(&reverse_handoff_ptr); 79 mailbox_init(); 80 enable_nonsecure_access(); 81 82 deassert_peripheral_reset(); 83 84 /* DDR and IOSSM driver init */ 85 agilex5_ddr_init(&reverse_handoff_ptr); 86 87 if (combo_phy_init(&reverse_handoff_ptr) != 0) { 88 ERROR("Combo Phy initialization failed\n"); 89 } 90 91 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 92 PLAT_BAUDRATE, &console); 93 94 /* Store magic number */ 95 // TODO: Temp workaround to ungate testing 96 // mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ); 97 98 if (!intel_mailbox_is_fpga_not_ready()) { 99 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK | 100 FPGA2SOC_MASK | F2SDRAM0_MASK); 101 } 102 } 103 104 void bl2_el3_plat_arch_setup(void) 105 { 106 handoff reverse_handoff_ptr; 107 unsigned long offset = 0; 108 109 struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, get_mmc_clk()); 110 111 mmc_info.mmc_dev_type = MMC_DEVICE_TYPE; 112 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 113 114 /* Request ownership and direct access to QSPI */ 115 mailbox_hps_qspi_enable(); 116 117 switch (boot_source) { 118 case BOOT_SOURCE_SDMMC: 119 NOTICE("SDMMC boot\n"); 120 sdmmc_init(&reverse_handoff_ptr, ¶ms, &mmc_info); 121 socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE); 122 break; 123 124 case BOOT_SOURCE_QSPI: 125 NOTICE("QSPI boot\n"); 126 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 127 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 128 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 129 if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) { 130 offset = PLAT_QSPI_DATA_BASE; 131 } 132 socfpga_io_setup(boot_source, offset); 133 break; 134 135 case BOOT_SOURCE_NAND: 136 NOTICE("NAND boot\n"); 137 nand_init(&reverse_handoff_ptr); 138 socfpga_io_setup(boot_source, PLAT_NAND_DATA_BASE); 139 break; 140 141 default: 142 ERROR("Unsupported boot source\n"); 143 panic(); 144 break; 145 } 146 } 147 148 uint32_t get_spsr_for_bl33_entry(void) 149 { 150 unsigned long el_status; 151 unsigned int mode; 152 uint32_t spsr; 153 154 /* Figure out what mode we enter the non-secure world in */ 155 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 156 el_status &= ID_AA64PFR0_ELX_MASK; 157 158 mode = (el_status) ? MODE_EL2 : MODE_EL1; 159 160 /* 161 * TODO: Consider the possibility of specifying the SPSR in 162 * the FIP ToC and allowing the platform to have a say as 163 * well. 164 */ 165 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 166 return spsr; 167 } 168 169 int bl2_plat_handle_post_image_load(unsigned int image_id) 170 { 171 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 172 173 assert(bl_mem_params); 174 175 #if SOCFPGA_SECURE_VAB_AUTH 176 /* 177 * VAB Authentication start here. 178 * If failed to authenticate, shall not proceed to process BL31 and hang. 179 */ 180 int ret = 0; 181 182 ret = socfpga_vab_init(image_id); 183 if (ret < 0) { 184 ERROR("SOCFPGA VAB Authentication failed\n"); 185 wfi(); 186 } 187 #endif 188 189 switch (image_id) { 190 case BL33_IMAGE_ID: 191 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 192 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 193 break; 194 default: 195 break; 196 } 197 198 return 0; 199 } 200 201 /******************************************************************************* 202 * Perform any BL3-1 platform setup code 203 ******************************************************************************/ 204 void bl2_platform_setup(void) 205 { 206 } 207