1 /* 2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/cadence/cdns_sdmmc.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/synopsys/dw_mmc.h> 18 #include <drivers/ti/uart/uart_16550.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 22 #include "agilex5_clock_manager.h" 23 #include "agilex5_ddr.h" 24 #include "agilex5_memory_controller.h" 25 #include "agilex5_mmc.h" 26 #include "agilex5_pinmux.h" 27 #include "agilex5_power_manager.h" 28 #include "agilex5_system_manager.h" 29 #include "ccu/ncore_ccu.h" 30 #include "combophy/combophy.h" 31 #include "nand/nand.h" 32 #include "qspi/cadence_qspi.h" 33 #include "sdmmc/sdmmc.h" 34 #include "socfpga_emac.h" 35 #include "socfpga_f2sdram_manager.h" 36 #include "socfpga_handoff.h" 37 #include "socfpga_mailbox.h" 38 #include "socfpga_private.h" 39 #include "socfpga_reset_manager.h" 40 #include "socfpga_ros.h" 41 #include "socfpga_vab.h" 42 #include "wdt/watchdog.h" 43 44 45 /* Declare mmc_info */ 46 static struct mmc_device_info mmc_info; 47 48 /* Declare cadence idmac descriptor */ 49 extern struct cdns_idmac_desc cdns_desc[8] __aligned(32); 50 51 const mmap_region_t agilex_plat_mmap[] = { 52 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 53 MT_MEMORY | MT_RW | MT_NS), 54 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, 55 MT_DEVICE | MT_RW | MT_NS), 56 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE), 58 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 59 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 60 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, 61 MT_DEVICE | MT_RW | MT_SECURE), 62 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 63 MT_DEVICE | MT_RW | MT_NS), 64 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, 65 MT_DEVICE | MT_RW | MT_SECURE), 66 {0}, 67 }; 68 69 boot_source_type boot_source = BOOT_SOURCE; 70 71 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 72 u_register_t x2, u_register_t x4) 73 { 74 static console_t console; 75 handoff reverse_handoff_ptr; 76 77 /* Enable nonsecure access for peripherals and other misc components */ 78 enable_nonsecure_access(); 79 80 /* Bring all the required peripherals out of reset */ 81 deassert_peripheral_reset(); 82 83 /* 84 * Initialize the UART console early in BL2 EL3 boot flow to get 85 * the error/notice messages wherever required. 86 */ 87 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 88 PLAT_BAUDRATE, &console); 89 90 /* Generic delay timer init */ 91 generic_delay_timer_init(); 92 93 socfpga_delay_timer_init(); 94 95 /* Get the handoff data */ 96 if ((socfpga_get_handoff(&reverse_handoff_ptr)) != 0) { 97 ERROR("BL2: Failed to get the correct handoff data\n"); 98 panic(); 99 } 100 101 config_clkmgr_handoff(&reverse_handoff_ptr); 102 /* Configure power manager PSS SRAM power gate */ 103 config_pwrmgr_handoff(&reverse_handoff_ptr); 104 105 /* Initialize the mailbox to enable communication between HPS and SDM */ 106 mailbox_init(); 107 108 /* DDR and IOSSM driver init */ 109 agilex5_ddr_init(&reverse_handoff_ptr); 110 111 if (combo_phy_init(&reverse_handoff_ptr) != 0) { 112 ERROR("Combo Phy initialization failed\n"); 113 } 114 115 /* Enable FPGA bridges as required */ 116 if (!intel_mailbox_is_fpga_not_ready()) { 117 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK | 118 FPGA2SOC_MASK | F2SDRAM0_MASK); 119 } 120 } 121 122 void bl2_el3_plat_arch_setup(void) 123 { 124 handoff reverse_handoff_ptr; 125 unsigned long offset = 0; 126 127 struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, get_mmc_clk()); 128 129 mmc_info.mmc_dev_type = MMC_DEVICE_TYPE; 130 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 131 132 /* Request ownership and direct access to QSPI */ 133 mailbox_hps_qspi_enable(); 134 135 switch (boot_source) { 136 case BOOT_SOURCE_SDMMC: 137 NOTICE("SDMMC boot\n"); 138 sdmmc_init(&reverse_handoff_ptr, ¶ms, &mmc_info); 139 socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE); 140 break; 141 142 case BOOT_SOURCE_QSPI: 143 NOTICE("QSPI boot\n"); 144 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 145 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 146 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 147 if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) { 148 offset = PLAT_QSPI_DATA_BASE; 149 } 150 socfpga_io_setup(boot_source, offset); 151 break; 152 153 case BOOT_SOURCE_NAND: 154 NOTICE("NAND boot\n"); 155 nand_init(&reverse_handoff_ptr); 156 socfpga_io_setup(boot_source, PLAT_NAND_DATA_BASE); 157 break; 158 159 default: 160 ERROR("Unsupported boot source\n"); 161 panic(); 162 break; 163 } 164 } 165 166 uint32_t get_spsr_for_bl33_entry(void) 167 { 168 unsigned long el_status; 169 unsigned int mode; 170 uint32_t spsr; 171 172 /* Figure out what mode we enter the non-secure world in */ 173 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 174 el_status &= ID_AA64PFR0_ELX_MASK; 175 176 mode = (el_status) ? MODE_EL2 : MODE_EL1; 177 178 /* 179 * TODO: Consider the possibility of specifying the SPSR in 180 * the FIP ToC and allowing the platform to have a say as 181 * well. 182 */ 183 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 184 return spsr; 185 } 186 187 int bl2_plat_handle_post_image_load(unsigned int image_id) 188 { 189 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 190 191 assert(bl_mem_params); 192 193 #if SOCFPGA_SECURE_VAB_AUTH 194 /* 195 * VAB Authentication start here. 196 * If failed to authenticate, shall not proceed to process BL31 and hang. 197 */ 198 int ret = 0; 199 200 ret = socfpga_vab_init(image_id); 201 if (ret < 0) { 202 ERROR("SOCFPGA VAB Authentication failed\n"); 203 wfi(); 204 } 205 #endif 206 207 switch (image_id) { 208 case BL33_IMAGE_ID: 209 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 210 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 211 break; 212 default: 213 break; 214 } 215 216 return 0; 217 } 218 219 /******************************************************************************* 220 * Perform any BL3-1 platform setup code 221 ******************************************************************************/ 222 void bl2_platform_setup(void) 223 { 224 } 225