refactor(tc): rename DPE header

The new name is more generic. The goal to add here
all platform dependent defines / data / config which
is DPE related.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>

refactor(tc): rename DPE header

The new name is more generic. The goal to add here
all platform dependent defines / data / config which
is DPE related.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I5b521932c45d8a9c43ea2344dde83c210801cfee

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Merge "refactor(tc): use the example CCA platform token from iat-verifier" into integration

Merge "feat(tc): add uart node in spmc manifest" into integration

fix(tc): add stubs for soc_css_init functions

Add TC specific stubs for both soc_css_init_nic400 and
soc_css_init_pcie. We do not require any initialisation of these
components for TC platforms.

Ch

fix(tc): add stubs for soc_css_init functions

Add TC specific stubs for both soc_css_init_nic400 and
soc_css_init_pcie. We do not require any initialisation of these
components for TC platforms.

Change-Id: If0129acd1050a56878cb9c3041a033192c88da57
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(fpga): enable new CPU features

Newer cores implemented in the FPGAs used by Arm Ltd. support more
ARMv9 features.

Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so
any us

feat(fpga): enable new CPU features

Newer cores implemented in the FPGAs used by Arm Ltd. support more
ARMv9 features.

Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so
any users of those features in lower ELs will not trigger a trap into
BL31.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Id99ecb7c5d6a25b77f7cc5fcad63f60027a4fd5a

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Merge "fix(fpga): avoid stripping kernel trampoline" into integration

fix(fpga): avoid stripping kernel trampoline

The Arm FPGA platform builds a final AXF file, which is an ELF file
containing some required trampolines and binaries, like the DTB. This is
more a "cont

fix(fpga): avoid stripping kernel trampoline

The Arm FPGA platform builds a final AXF file, which is an ELF file
containing some required trampolines and binaries, like the DTB. This is
more a "container with load addresses" than an object or executable
file, but it's still built with the linker tool.
Commit acf0076ae2e5 ("build(fpga): correctly handle gcc as linker for
LTO") pulled in ${TF_LDFLAGS} when building this AXF file, which
includes "--gc-sections". That strips the kernel trampoline off that
file, making the board hang when the kernel is loaded at 0x80200000
(the recommended load address for "newer" kernels).

Drop the usage of TF_LDFLAGS altogether, since we need none of the
options specified there for our special linker step. Instead collect
the needed options (like -nostdlib) in a separate variable, and just
account for the slight syntax differences between GCC and clang.
"--strip-debug" turns out to be redundant, since "-s" already strips
more symbols, so remove that from the list.

Change-Id: I1349d58fa93973ba3add8cab2272259abdea84e0
Fixes: acf0076ae2e5 ("build(fpga): correctly handle gcc as linker for LTO")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "feat(corstone1000): add multicore support for fvp" into integration

Merge "refactor(dice): save parent context handle" into integration

feat(tc): add uart node in spmc manifest

The device memory described in the SP manifest has to be described in
the SPMC manifest as well. In this case, OP-TEE includes this UART
device in its SP man

feat(tc): add uart node in spmc manifest

The device memory described in the SP manifest has to be described in
the SPMC manifest as well. In this case, OP-TEE includes this UART
device in its SP manifest. Hence, this commit adds it in the SPMC
manifest.

Change-Id: I0f84d7b105c072dd021f0f2d215adf6bcdf5f98f
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "ip_smmu" into integration

* changes:
feat(tc): bind SMMU-600 with the DPU on TC3 FPGA
feat(tc): bind SMMU-700 with DPU on TC3
refactor(tc): append binding for SMMU-700

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the secondary cores.

Change-Id: Ie66b3dc43abadec88323999052357e2a9cdfd950
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

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Merge "feat(fvp): add cpu power control" into integration

refactor(tc): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software componen

refactor(tc): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software components, and to
provide a more realistic breakdown of the expected components in the CCA
TCB.

This change replaces the static CCA platform token in the Total Compute
platform.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493

Change-Id: I792e693cc994fc1e856f713fd97bac4930b28e1e
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>

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Merge "fix(tc): add SCP_BL2 to RSE measured boot" into integration

feat(fvp): add cpu power control

Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from

feat(fvp): add cpu power control

Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from CPU Power control.

However there are certain older CPU's that don't have DSU and
don't support CPUPWRCTRL_EL1, so populate them as a list
and ignore setting core-off bit for those older CPU's as all newer
CPU's have them.

Note: unfortunately there is no mechanism to identify if a DSU is
present and CPUPWRCTRL_EL1 is supported through any CPU control
registers and CPUPWRCTRL_EL1 is supported only for ARM64 platforms
and not available in ARM32 platforms.

Change-Id: Iba6c3c8db60dbeb177cead7ebc65df8265860da7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables

build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables are boolean values determining
whether the build system has been configured to run silently or
verbosely respectively (i.e. with `--silent` or `V=1`).

These two modes cannot be used together - if `silent` is truthy then
`verbose` is always falsy. As such:

make --silent V=1

... results in a silent build.

In addition to these boolean variables, we also introduce two new
variables - `s` and `q` - for use in rule recipes to conditionally
suppress the output of commands.

When building silently, `s` expands to a value which disables the
command that follows, and `q` expands to a value which supppresses
echoing of the command:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed but not echoed'

When building verbosely, `s` expands to a value which disables the
command that follows, and `q` expands to nothing:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed and echoed'

In all other cases, both `s` and `q` expand to a value which suppresses
echoing of the command that follows:

$(s)echo 'This command is executed but not echoed'
$(q)echo 'This command is executed but not echoed'

The `s` variable is predominantly useful for `echo` commands, where you
always want to suppress echoing of the command itself, whilst `q` is
more useful for all other commands.

Change-Id: I8d8ff6ed714d3cb401946c52955887ed7dca602b
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure acces

Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure access to pmu counters on TC3

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refactor(dice): save parent context handle

Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core execut

refactor(dice): save parent context handle

Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core executes the DPE service
remains up and running. In this case, client needs to save
a valid context handle to be able to send commands again
to the DPE service during the new boot sequence.

BL1 saves a valid parent context handle to SDS
before passing the execution to BL2. This handle
can be used in case of a restart scenario when AP
is restarted but RSE is not. Because in that case
RSE does not save an initial context handle to SDS,
which meant to be used by AP during the boot process.

By then the very first initial context handle is
invalidated because it was already used in the
previous boot cycle by BL1.

BL2 does not need to do this, because the cold
boot starts with BL1.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Id14eefd2ec758f89f672af176e4f5386a397fa35

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Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch

Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch attestation key and token from RSE
feat(psa): introduce generic library for CCA attestation
feat(rdfremont): initialize the rse comms driver
feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3
fix(rse): include lib-psa to resolve build
feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms
feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms
feat(rdfremont): initialize GPT on GPC SMMU block
feat(rdfremont): update Root registers page offset for SMMUv3
feat(rdfremont): enable MTE2 if present on the platform
feat(rdfremont): enable SVE for SWD and NS
feat(rdfremont): enable AMU if present on the platform
feat(rdfremont): enable MPAM if present on the platform
feat(rdfremont): add DRAM pas entries in pas table for multichip
feat(rdfremont): add implementation for GPT setup
feat(rdfremont): integrate DTS files for RD-Fremont variants
feat(rdfremont): add support for RD-Fremont-Cfg2
feat(rdfremont): add support for RD-Fremont-Cfg1
feat(rdfremont): add support for RD-Fremont
feat(neoverse-rd): add scope for RD-Fremont variants
feat(neoverse-rd): add multichip pas entries
feat(neoverse-rd): add pas definitions for third gen platforms
feat(neoverse-rd): add DRAM layout for third gen platforms
feat(neoverse-rd): add SRAM layout for third gen platforms
feat(neoverse-rd): add firmware definitions for third gen platforms
feat(neoverse-rd): add RoS definitions for third gen platforms
feat(neoverse-rd): add CSS definitions for third gen platforms

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fix(tc): add SCP_BL2 to RSE measured boot

SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.

fix(tc): add SCP_BL2 to RSE measured boot

SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic87743564136f03a901c90ff1ec614f5965b9a47

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Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB suppo

Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB support
feat(dt-bindings): introduce Dualroot CoT DTB

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feat(rdfremont): add support for measured boot at BL1 and BL2

RD-Fremont platforms include Runtime Security Engine (RSE) as the
hardware crypto module. Add rse_measured_boot driver based platform
ho

feat(rdfremont): add support for measured boot at BL1 and BL2

RD-Fremont platforms include Runtime Security Engine (RSE) as the
hardware crypto module. Add rse_measured_boot driver based platform
hooks to measure and record firmware image measurements.

Additionally, add support for measured boot at BL1 and BL2 boot stages
on RD-Fremont platforms. The patch adds the RSE measured boot metadata
that includes firmware image IDs, measurement slot number and other
information. It also initializes the AP communication with RSE over
AP-RSE root MHUv3 channel to pass firmware image measurements to RSE to
support extended measurements.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ia1b0bf673e865b31862cb8af79c4c71a5ba4dbea

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feat(arm): mock support for CCA NV ctr

Arm reference design FVP platforms such as RD-Fremont do not implement
the CCA_FW_NVCOUNTER. Update firmware such that the implementation will
return TRUSTED_F

feat(arm): mock support for CCA NV ctr

Arm reference design FVP platforms such as RD-Fremont do not implement
the CCA_FW_NVCOUNTER. Update firmware such that the implementation will
return TRUSTED_FW_NVCOUNTER when the caller requests the CCA NV counter.
This allows the platforms to use the CCA CoT on FVP platforms.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ifab724fae63857056b3eeb44eeefc15c4c610eed

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feat(rdfremont): fetch attestation key and token from RSE

Use the delegated attestation driver to fetch platform attestation token
and Realm attestation key from RSE over the AP-RSE comms interface.

feat(rdfremont): fetch attestation key and token from RSE

Use the delegated attestation driver to fetch platform attestation token
and Realm attestation key from RSE over the AP-RSE comms interface.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Id0cfd82ef79598cd8368ba017c145bf34d502e65

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