refactor(tc): use internal trusted storage

Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secu

refactor(tc): use internal trusted storage

Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secure storage and adding support for the
internal trusted storage.

And enable external SP images in BL2 config for TC, so that
we do not have to modify this file whenever the list of SPs
changes. It is already implemented for fvp in the below commit.

commit 33993a3737737a03ee5a9d386d0a027bdc947c9c
Author: Balint Dobszay <balint.dobszay@arm.com>
Date: Fri Mar 26 15:19:11 2021 +0100

feat(fvp): enable external SP images in BL2 config

Change-Id: I3e0a0973df3644413ca5c3a32f36d44c8efd49c7
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

show more ...

Merge changes from topic "gic-700-auto" into integration

* changes:
feat(arm_fpga): support GICv4 images
feat(gicv3): detect GICv4 feature at runtime
feat(gicv3): multichip: detect GIC-700 at

Merge changes from topic "gic-700-auto" into integration

* changes:
feat(arm_fpga): support GICv4 images
feat(gicv3): detect GICv4 feature at runtime
feat(gicv3): multichip: detect GIC-700 at runtime
refactor(gic): move GIC IIDR numbers
refactor(gicv3): rename GIC Clayton to GIC-700

show more ...

Merge changes I0ae8a6ea,I0b4fc83e into integration

* changes:
feat(tc): Enable SVE for both secure and non-secure world
feat(tc): populate HW_CONFIG in BL31

feat(tc): Enable SVE for both secure and non-secure world

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0ae8a6ea3245373a17af76c9b7dc3f38f3711091

feat(tc): populate HW_CONFIG in BL31

BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate

feat(tc): populate HW_CONFIG in BL31

BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate fconf.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0b4fc83e6e0a0b9401f692516654eb9a3b037616

show more ...

Merge "feat(fvp): enable external SP images in BL2 config" into integration

Merge "feat(board/rdn2): add tzc master source ids for soc dma" into integration

fix(arm_fpga): reserve BL31 memory

Embarrassingly we never told the non-secure world that secure firmware
lives in the first few hundred KBs of DRAM, so any non-secure payload
could happily overwrit

fix(arm_fpga): reserve BL31 memory

Embarrassingly we never told the non-secure world that secure firmware
lives in the first few hundred KBs of DRAM, so any non-secure payload
could happily overwrite TF-A, and we couldn't even blame it.

Advertise the BL31 region in the reserved-memory DT node, so non-secure
world stays out of it.

This fixes Linux booting on FPGAs with less memory than usual.

Change-Id: I7fbe7d42c0b251c0ccc43d7c50ca902013d152ec
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

fix(arm_fpga): limit BL31 memory usage

At the moment we specified the BL31 memory limits to 1MB; since we
typically have gigabytes of DRAM, we can be quite generous.

However the default parameters

fix(arm_fpga): limit BL31 memory usage

At the moment we specified the BL31 memory limits to 1MB; since we
typically have gigabytes of DRAM, we can be quite generous.

However the default parameters expect the devicetree binary at
0x80070000, so we should actually make sure we have no code or data
beyond that point.

Limit the ARM FPGA BL31 memory footprint to this available 7*64K region.
We stay within the limit at the moment, with more than half of it
reserved for stacks, so this could be downsized later should we run
into problems.

The PIE addresses stay as they are, since the default addresses do not
apply there anywhere, and the build is broken anyway.

Change-Id: I7768af1a93ff67096f4359fc5f5feb66464bafaa
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

feat(fvp): enable external SP images in BL2 config

Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Ser

feat(fvp): enable external SP images in BL2 config

Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Services). This commit implements a workaround to enable adding
SP UUIDs to the list at build time.

Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: Iff85d3778596d23d777dec458f131bd7a8647031

show more ...

feat(arm_fpga): support GICv4 images

Up until now we relied on the GICs used in our FPGA images to be GICv3
compliant, without the "direct virtual injection" feature (aka GICv4)
enabled.
To support

feat(arm_fpga): support GICv4 images

Up until now we relied on the GICs used in our FPGA images to be GICv3
compliant, without the "direct virtual injection" feature (aka GICv4)
enabled.
To support newer images which have GICv4 compliant GICs, enable the
newly introduced GICv4 detection code, and use that also when we adjust
the redistributor region size in the devicetree.

This allows the same BL31 image to be used with GICv3 or GICv4 FPGA
images.

Change-Id: I9f6435a6d5150983625efe3650a8b7d1ef11b1d1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec

feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec or not. This just changes the number of 64K MMIO pages
we expect per redistributor.

To support firmware builds which run on variable systems (emulators,
fast model or FPGAs), let's make this decision at runtime.
The GIC specification provides several architected flags to learn the
size of the MMIO frame per redistributor, we use GICR_TYPER[VLPI] here.

Provide a (static inline) function to return the size of each
redistributor.
We keep the GIC_ENABLE_V4_EXTN build time variable around, but change
its meaning to enable this autodetection code. Systems not defining this
rely on a "pure" GICv3 (as before), but platforms setting it to "1" can
now deal with both configurations.

Change-Id: I9ede4acf058846157a0a9e2ef6103bf07c7655d9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

feat(plat/fvp): enable trace extension features by default

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I3e344b0abda7ab4e54ee918ec65ff39d40855fcd

Merge "cpu: add support for Demeter CPU" into integration

feat(board/rdn2): add tzc master source ids for soc dma

Add TZC master source id for DMA in the SoC space and for the DMAs
behind the I/O Virtualization block to allow the non-secure transactions
fr

feat(board/rdn2): add tzc master source ids for soc dma

Add TZC master source id for DMA in the SoC space and for the DMAs
behind the I/O Virtualization block to allow the non-secure transactions
from these DMAs targeting DRAM.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I77a2947b01b4b49a7c1940f09cf62b7b5257657c

show more ...

refactor(gicv3): rename GIC Clayton to GIC-700

The GIC IP formerly known as "GIC Clayton" has been released under the
name of "GIC-700".

Rename occurences of Clayton in comments and macro names to

refactor(gicv3): rename GIC Clayton to GIC-700

The GIC IP formerly known as "GIC Clayton" has been released under the
name of "GIC-700".

Rename occurences of Clayton in comments and macro names to reflect the
official name.

Change-Id: Ie8c55f7da7753127d58c8382b0033c1b486f7909
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

Merge "fix(plat/arm_fpga): enable AMU extension" into integration

cpu: add support for Demeter CPU

This patch adds the basic CPU library code to support the Demeter
CPU. This CPU is based on the Makalu-ELP core so that CPU lib code
was adapted to create this patc

cpu: add support for Demeter CPU

This patch adds the basic CPU library code to support the Demeter
CPU. This CPU is based on the Makalu-ELP core so that CPU lib code
was adapted to create this patch.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib5740b748008a72788c557f0654d8d5e9ec0bb7f

show more ...

fix(plat/arm_fpga): enable AMU extension

As done recently for plat/tc0 in b5863cab9, enable AMU explicitly.
This is necessary as the recent changes that enable SVE for the secure
world disable AMU b

fix(plat/arm_fpga): enable AMU extension

As done recently for plat/tc0 in b5863cab9, enable AMU explicitly.
This is necessary as the recent changes that enable SVE for the secure
world disable AMU by default in the CPTR_EL3 reset value.

Change-Id: Ie3abf1dee8a4e1c8c39f934da8e32d67891f5f09
Signed-off-by: Tom Cosgrove <tom.cosgrove@arm.com>

show more ...

feat: enabling stack protector for diphda

This commit activates the stack protector feature for the diphda
platform.

Change-Id: Ib16b74871c62b67e593a76ecc12cd3634d212614
Signed-off-by: Abdellatif E

feat: enabling stack protector for diphda

This commit activates the stack protector feature for the diphda
platform.

Change-Id: Ib16b74871c62b67e593a76ecc12cd3634d212614
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

show more ...

feat(plat/arm): Introduce TC1 platform

This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.

Signed-off-by: U

feat(plat/arm): Introduce TC1 platform

This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd

show more ...

feat(ff-a): update FF-A version to v1.1

Bump the required FF-A version in framework and manifests to v1.1 as
upstream feature development goes.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com

feat(ff-a): update FF-A version to v1.1

Bump the required FF-A version in framework and manifests to v1.1 as
upstream feature development goes.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I89b2bd3828a13fc4344ccd53bc3ac9c0c22ab29f

show more ...

Merge "feat(ff-a): change manifest messaging method" into integration

fix(plat/fvp): provide boot files via semihosting

These files are needed during boot, but they were missing
for semihosting.
With this patch, the list of files is complete enough to
boot on ATF plat

fix(plat/fvp): provide boot files via semihosting

These files are needed during boot, but they were missing
for semihosting.
With this patch, the list of files is complete enough to
boot on ATF platform via semihosting.

Change-Id: I2f0ca25983a6e18096f040780776f19f8040ea79
Signed-off-by: stsp@users.sourceforge.net

show more ...

Merge changes from topic "sve+amu" into integration

* changes:
fix(plat/tc0): enable AMU extension
fix(el3_runtime): fix SVE and AMU extension enablement flags