fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which v

fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which verified this feature.

BREAKING CHANGE: platforms can no longer retrieve the host ROTPK from
the RSE as these are no longer provisioned.

Change-Id: I2c852855e53c36e77f639f17f4c181290d95ccff
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.

Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link

feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I6e97954a1ce91fdbda4edcdba5ccfa1d7c8ff475

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chore(tc): remove TC2 platform variant

Remove TC2 platform support which was deprecated in the last release.

Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <M

chore(tc): remove TC2 platform variant

Remove TC2 platform support which was deprecated in the last release.

Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(tc): port BL31-BL33 interface to firmware handoff framework

Adding support for this framework at the handoff boundary between
firmware stage BL31 and BL33 on TC.

Signed-off-by: Jayanth Dodderi

feat(tc): port BL31-BL33 interface to firmware handoff framework

Adding support for this framework at the handoff boundary between
firmware stage BL31 and BL33 on TC.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ia6cd29c8b6cdda0a127a3bac02f6fa1dcfc07151

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feat(tc): port BL1-BL2 interface to firmware handoff framework

The firmware handoff framework, is a light weight mechanism for
sharing information between bootloader stages.
Adding support for this

feat(tc): port BL1-BL2 interface to firmware handoff framework

The firmware handoff framework, is a light weight mechanism for
sharing information between bootloader stages.
Adding support for this framework at the handoff boundary between
firmware stage BL1 and BL2 on TC.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Iae13adbcdd6ebbdcc61d04e017655c6b8d715ea0

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refactor(tc): add plat_rse_comms_init

The same way it is done for neoverse_rd, create a plat_rse_comms_init()
function to call rse_comms_init().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Ch

refactor(tc): add plat_rse_comms_init

The same way it is done for neoverse_rd, create a plat_rse_comms_init()
function to call rse_comms_init().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I12f3b8a38a5369decb4b97f8aceeb0dc81cbea28

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Merge "fix(tc): enable Last-level cache (LLC) for tc4" into integration

fix(tc): enable Last-level cache (LLC) for tc4

EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,

External L

fix(tc): enable Last-level cache (LLC) for tc4

EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,

External LLC is present on TC4 systems in MCN but it is not enabled in
CPU registers so enable it.

On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC
so take care of that as well.

Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM

Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.

Change-Id: I70b68b06501d17dcebbe78bee8fec0a70

refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM

Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.

Change-Id: I70b68b06501d17dcebbe78bee8fec0a701106c92
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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feat(tc): configure UART for TC4 FPGA

TC4 FPGA have a UART clock of 4000000 so modify the value
of TC_UARTCLK for TC4.

Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28
Signed-off-by: Jagdish Ge

feat(tc): configure UART for TC4 FPGA

TC4 FPGA have a UART clock of 4000000 so modify the value
of TC_UARTCLK for TC4.

Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): set console baurate to 38400 for fvp as well

Set console baurate to 38400 for fvp as well for code
simplicity.

Change-Id: I58ba6b7043541f6eb67e32257307da4eba0bb28a
Signed-off-by: Jagdish G

fix(tc): set console baurate to 38400 for fvp as well

Set console baurate to 38400 for fvp as well for code
simplicity.

Change-Id: I58ba6b7043541f6eb67e32257307da4eba0bb28a
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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refactor(tc): remove redundant macro UARTCLK_FREQ

remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.

Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagd

refactor(tc): remove redundant macro UARTCLK_FREQ

remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.

Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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feat(tc): define MCN related macros for TC4

Define MCN related macros for TC4 to add TC4 specific MCN PMU
nodes in dts and to enable MCN PMU NS access in further commits.

Signed-off-by: Jagdish Ged

feat(tc): define MCN related macros for TC4

Define MCN related macros for TC4 to add TC4 specific MCN PMU
nodes in dts and to enable MCN PMU NS access in further commits.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ifc02fcd833888a9953fac404585468316aa0168c

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feat(tc): enable DSU PMU el1 access for TC4

Enable DSU PMU EL1 access for TC4 to use DSU PMU using perf
in Linux.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <

feat(tc): enable DSU PMU el1 access for TC4

Enable DSU PMU EL1 access for TC4 to use DSU PMU using perf
in Linux.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I5492bab5c95d60ffaaede4606d8d75c00f988eb6

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feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554

feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loadi

feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loading Android image

Change-Id: I5ec82646cb2993e7b5976e702ebcc8efa51d1128
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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Merge "chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default" into integration

feat(tc): increase SCP BL2 size to support optimization 0

It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.

Signed-o

feat(tc): increase SCP BL2 size to support optimization 0

It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib416c89226475d44746a7561dd949a14349c3e4b

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chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default

Previously we only enabled 8GB unless we were loading the filesystem
from RAM.

Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
S

chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default

Previously we only enabled 8GB unless we were loading the filesystem
from RAM.

Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): retain NS timer frame ID for TC2 as 0

Recent change [1], caused failure in the TC2 run and this
change meant to be for TC3 and TC4.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-f

fix(tc): retain NS timer frame ID for TC2 as 0

Recent change [1], caused failure in the TC2 run and this
change meant to be for TC3 and TC4.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/31424

Change-Id: Ibfd604a842815bcf6d413dcba2c440df81dbb486
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "add-qcbor-dependency" into integration

* changes:
chore(tc): increase stack size with 0x100 bytes
chore(tc): link QCBOR library to the platform test