1 /* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <cortex_a520.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/board_css_def.h> 14 #include <plat/arm/board/common/v2m_def.h> 15 16 /* 17 * arm_def.h depends on the platform system counter macros, so must define the 18 * platform macros before including arm_def.h. 19 */ 20 #if TARGET_PLATFORM == 4 21 #ifdef ARM_SYS_CNTCTL_BASE 22 #error "error: ARM_SYS_CNTCTL_BASE is defined prior to the PLAT_ARM_SYS_CNTCTL_BASE definition" 23 #endif 24 #define PLAT_ARM_SYS_CNTCTL_BASE UL(0x47000000) 25 #define PLAT_ARM_SYS_CNTREAD_BASE UL(0x47010000) 26 #endif 27 28 #include <plat/arm/common/arm_def.h> 29 30 #include <plat/arm/common/arm_spm_def.h> 31 #include <plat/arm/css/common/css_def.h> 32 #include <plat/arm/soc/common/soc_css_def.h> 33 #include <plat/common/common_def.h> 34 35 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 36 37 /* 38 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 39 * its base is ARM_AP_TZC_DRAM1_BASE. 40 * 41 * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: 42 * - BL32_BASE when SPD_spmd is enabled 43 * - Region to load secure partitions 44 * 45 * 46 * 0x8000_0000 ------------------ TC_NS_DRAM1_BASE 47 * | DTB | 48 * | (32K) | 49 * 0x8000_8000 ------------------ 50 * | NT_FW_CONFIG | 51 * | (4KB) | 52 * 0x8000_9000 ------------------ 53 * | ... | 54 * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE 55 * | OP-TEE shmem | 56 * | (2MB) | 57 * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE 58 * | | 59 * | SPMC | 60 * | SP | 61 * | (96MB) | 62 * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE 63 * | AP | 64 * | EL3 Monitor | 65 * | SCP | 66 * | (16MB) | 67 * 0xFFFF_FFFF ------------------ 68 * 69 * 70 */ 71 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 72 TC_TZC_DRAM1_SIZE) 73 #define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */ 74 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 75 TC_TZC_DRAM1_SIZE - 1) 76 77 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 78 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 79 ARM_TZC_DRAM1_SIZE - \ 80 TC_TZC_DRAM1_SIZE) 81 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1) 82 83 #define TC_NS_OPTEE_SIZE (2 * SZ_1M) 84 #define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE) 85 86 /* 87 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 88 */ 89 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 90 TC_NS_DRAM1_BASE, \ 91 TC_NS_DRAM1_SIZE, \ 92 MT_MEMORY | MT_RW | MT_NS) 93 94 95 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 96 TC_TZC_DRAM1_BASE, \ 97 TC_TZC_DRAM1_SIZE, \ 98 MT_MEMORY | MT_RW | MT_SECURE) 99 100 #define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE 101 #define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000) 102 103 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 104 PLAT_HW_CONFIG_DTB_BASE, \ 105 PLAT_ARM_HW_CONFIG_SIZE, \ 106 MT_MEMORY | MT_RO | MT_NS) 107 /* 108 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 109 * max size of BL32 image. 110 */ 111 #if defined(SPD_spmd) 112 #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) 113 114 #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR 115 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 116 #endif 117 118 /* 119 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 120 * plat_arm_mmap array defined for each BL stage. 121 */ 122 #if defined(IMAGE_BL31) 123 # if SPM_MM 124 # define PLAT_ARM_MMAP_ENTRIES 9 125 # define MAX_XLAT_TABLES 7 126 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 127 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 128 # else 129 # define PLAT_ARM_MMAP_ENTRIES 8 130 # define MAX_XLAT_TABLES 8 131 # endif 132 #elif defined(IMAGE_BL32) 133 # define PLAT_ARM_MMAP_ENTRIES 8 134 # define MAX_XLAT_TABLES 5 135 #elif !USE_ROMLIB 136 # define PLAT_ARM_MMAP_ENTRIES 11 137 # define MAX_XLAT_TABLES 7 138 #else 139 # define PLAT_ARM_MMAP_ENTRIES 12 140 # define MAX_XLAT_TABLES 6 141 #endif 142 143 /* 144 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 145 * plus a little space for growth. 146 */ 147 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 148 149 /* 150 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 151 */ 152 153 #if USE_ROMLIB 154 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 155 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 156 #else 157 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 158 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 159 #endif 160 161 /* 162 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 163 * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT 164 * and MEASURED_BOOT is enabled. 165 */ 166 # define PLAT_ARM_MAX_BL2_SIZE 0x29000 167 168 169 /* 170 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 171 * calculated using the current BL31 PROGBITS debug size plus the sizes of 172 * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and 173 * MEASURED_BOOT is enabled. 174 */ 175 #define PLAT_ARM_MAX_BL31_SIZE 0x60000 176 177 /* 178 * Size of cacheable stacks 179 */ 180 #if defined(IMAGE_BL1) 181 # define PLATFORM_STACK_SIZE 0x1000 182 #elif defined(IMAGE_BL2) 183 # define PLATFORM_STACK_SIZE 0x1000 184 #elif defined(IMAGE_BL2U) 185 # define PLATFORM_STACK_SIZE 0x400 186 #elif defined(IMAGE_BL31) 187 # if SPM_MM 188 # define PLATFORM_STACK_SIZE 0x500 189 # else 190 # define PLATFORM_STACK_SIZE 0xb00 191 # endif 192 #elif defined(IMAGE_BL32) 193 # define PLATFORM_STACK_SIZE 0x440 194 #endif 195 196 /* 197 * In the current implementation the RoT Service request that requires the 198 * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 199 * maximum required buffer size is calculated based on the platform-specific 200 * needs of this request. 201 */ 202 #define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE 0x500 203 204 #define TC_DEVICE_BASE 0x21000000 205 #define TC_DEVICE_SIZE 0x5f000000 206 207 #if defined(TARGET_FLAVOUR_FPGA) 208 #undef V2M_FLASH0_BASE 209 #undef V2M_FLASH0_SIZE 210 #define V2M_FLASH0_BASE UL(0x0C000000) 211 #define V2M_FLASH0_SIZE UL(0x02000000) 212 #endif 213 214 // TC_MAP_DEVICE covers different peripherals 215 // available to the platform 216 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 217 TC_DEVICE_BASE, \ 218 TC_DEVICE_SIZE, \ 219 MT_DEVICE | MT_RW | MT_SECURE) 220 221 222 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 223 V2M_FLASH0_SIZE, \ 224 MT_DEVICE | MT_RO | MT_SECURE) 225 #if TARGET_PLATFORM == 2 226 #define PLAT_ARM_NSTIMER_FRAME_ID U(0) 227 #else 228 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 229 #endif 230 231 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 232 233 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 234 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 235 236 #define PLAT_ARM_NSRAM_BASE 0x06000000 237 #if TARGET_FLAVOUR_FVP 238 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 239 #else /* TARGET_FLAVOUR_FPGA */ 240 #define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */ 241 #endif /* TARGET_FLAVOUR_FPGA */ 242 243 #if TARGET_PLATFORM <= 2 244 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 245 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 246 #elif TARGET_PLATFORM >= 3 247 248 #if TC_FPGA_ANDROID_IMG_IN_RAM 249 /* 10GB reserved for system+userdata+vendor images */ 250 #define SYSTEM_IMAGE_SIZE 0xC0000000 /* 3GB */ 251 #define USERDATA_IMAGE_SIZE 0x140000000 /* 5GB */ 252 #define VENDOR_IMAGE_SIZE 0x20000000 /* 512MB */ 253 #define RESERVE_IMAGE_SIZE 0x60000000 /* 1.5GB */ 254 #define ANDROID_FS_SIZE (SYSTEM_IMAGE_SIZE + \ 255 USERDATA_IMAGE_SIZE + \ 256 VENDOR_IMAGE_SIZE + RESERVE_IMAGE_SIZE) 257 258 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) + ANDROID_FS_SIZE 259 #define PLAT_ARM_DRAM2_SIZE ULL(0x380000000) - ANDROID_FS_SIZE 260 #else 261 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 262 #define PLAT_ARM_DRAM2_SIZE ULL(0x380000000) 263 #endif /* TC_FPGA_ANDROID_IMG_IN_RAM */ 264 265 #endif /* TARGET_VERSION >= 3 */ 266 267 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) 268 269 #define TC_NS_MTE_SIZE (256 * SZ_1M) 270 /* the SCP puts the carveout at the end of DRAM2 */ 271 #define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE) 272 273 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) 274 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ 275 INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ 276 GIC_HIGHEST_SEC_PRIORITY, grp, \ 277 GIC_INTR_CFG_LEVEL) 278 279 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 280 PLAT_SP_IMAGE_NS_BUF_SIZE) 281 282 #define PLAT_ARM_SP_MAX_SIZE U(0x2000000) 283 284 /******************************************************************************* 285 * Memprotect definitions 286 ******************************************************************************/ 287 /* PSCI memory protect definitions: 288 * This variable is stored in a non-secure flash because some ARM reference 289 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 290 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 291 */ 292 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 293 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 294 295 /* Secure Watchdog Constants */ 296 #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) 297 #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) 298 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 299 #define SBSA_SECURE_WDOG_INTID 86 300 301 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 302 303 /* Index of SDS region used in the communication with SCP */ 304 #define SDS_SCP_AP_REGION_ID U(0) 305 /* Index of SDS region used in the communication with RSE */ 306 #define SDS_RSE_AP_REGION_ID U(1) 307 /* 308 * Memory region for RSE's shared data storage (SDS) 309 * It is placed right after the SCMI payload area. 310 */ 311 #define PLAT_ARM_RSE_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \ 312 CSS_SCMI_PAYLOAD_SIZE_MAX) 313 314 #define PLAT_ARM_CLUSTER_COUNT U(1) 315 #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 316 #define PLAT_MAX_CPUS_PER_CLUSTER U(14) 317 #else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 318 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 319 #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 320 #define PLAT_MAX_PE_PER_CPU U(1) 321 322 #define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT) 323 324 /* Message Handling Unit (MHU) base addresses */ 325 #if TARGET_PLATFORM <= 2 326 #define PLAT_CSS_MHU_BASE UL(0x45400000) 327 #elif TARGET_PLATFORM >= 3 328 #define PLAT_CSS_MHU_BASE UL(0x46000000) 329 #endif /* TARGET_PLATFORM >= 3 */ 330 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 331 332 /* AP<->RSS MHUs */ 333 #if TARGET_PLATFORM <= 2 334 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000) 335 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000) 336 #elif TARGET_PLATFORM == 3 337 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) 338 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000) 339 #elif TARGET_PLATFORM == 4 340 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) 341 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49010000) 342 #endif 343 344 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 345 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 346 347 /* 348 * Physical and virtual address space limits for MMU in AARCH64 349 */ 350 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 351 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 352 353 /* GIC related constants */ 354 #define PLAT_ARM_GICD_BASE UL(0x30000000) 355 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 356 #define PLAT_ARM_GICR_BASE UL(0x30080000) 357 358 /* 359 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 360 * SCP_BL2 size plus a little space for growth. 361 */ 362 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x30000 363 364 /* 365 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 366 * SCP_BL2U size plus a little space for growth. 367 */ 368 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x30000 369 370 #if TARGET_PLATFORM <= 2 371 /* TZC Related Constants */ 372 #define PLAT_ARM_TZC_BASE UL(0x25000000) 373 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 374 375 #define TZC400_OFFSET UL(0x1000000) 376 #define TZC400_COUNT 4 377 378 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 379 (n * TZC400_OFFSET)) 380 381 #define TZC_NSAID_DEFAULT U(0) 382 383 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 384 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 385 386 /* 387 * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to 388 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as 389 * secure. The second and third regions gives non secure access to rest of DRAM. 390 */ 391 #define TC_TZC_REGIONS_DEF \ 392 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 393 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 394 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 395 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 396 {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ 397 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 398 #endif 399 400 /* virtual address used by dynamic mem_protect for chunk_base */ 401 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 402 403 #if ARM_GPT_SUPPORT 404 /* 405 * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. 406 * Offset of the FIP in the GPT image. BL1 component uses this option 407 * as it does not load the partition table to get the FIP base 408 * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) 409 * (i.e. after reserved sectors 0-47). 410 * Offset = 48 * 512 = 0x6000 411 */ 412 #undef PLAT_ARM_FIP_OFFSET_IN_GPT 413 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 414 #endif /* ARM_GPT_SUPPORT */ 415 416 /* UART related constants */ 417 418 #define TC_UART0 0x2a400000 419 #define TC_UART1 0x2a410000 420 421 /* 422 * TODO: if any more undefs are needed, it's better to consider dropping the 423 * board_css_def.h include above 424 */ 425 #undef PLAT_ARM_BOOT_UART_BASE 426 #undef PLAT_ARM_RUN_UART_BASE 427 428 #undef PLAT_ARM_CRASH_UART_BASE 429 #undef PLAT_ARM_BOOT_UART_CLK_IN_HZ 430 #undef PLAT_ARM_RUN_UART_CLK_IN_HZ 431 432 #if TARGET_FLAVOUR_FVP 433 #define PLAT_ARM_BOOT_UART_BASE TC_UART1 434 #define TC_UARTCLK 7372800 435 #else /* TARGET_FLAVOUR_FPGA */ 436 #define PLAT_ARM_BOOT_UART_BASE TC_UART0 437 #if TARGET_PLATFORM <= 2 438 #define TC_UARTCLK 5000000 439 #elif TARGET_PLATFORM >= 3 440 #define TC_UARTCLK 3750000 441 #endif /* TARGET_PLATFORM >= 3 */ 442 #undef ARM_CONSOLE_BAUDRATE 443 #define ARM_CONSOLE_BAUDRATE 38400 444 #endif /* TARGET_FLAVOUR_FPGA */ 445 446 #define PLAT_ARM_RUN_UART_BASE TC_UART0 447 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 448 449 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK 450 #define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK 451 452 #if TARGET_PLATFORM == 3 453 #define NCI_BASE_ADDR UL(0x4F000000) 454 #ifdef TARGET_FLAVOUR_FPGA 455 #define MCN_ADDRESS_SPACE_SIZE 0x00120000 456 #else 457 #define MCN_ADDRESS_SPACE_SIZE 0x00130000 458 #endif /* TARGET_FLAVOUR_FPGA */ 459 #define MCN_OFFSET_IN_NCI 0x00C90000 460 #define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI) 461 #define MCN_PMU_OFFSET 0x000C4000 462 #define MCN_MICROARCH_OFFSET 0x000E4000 463 #define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET) 464 #define MCN_SCR_OFFSET 0x4 465 #define MCN_SCR_PMU_BIT 10 466 #define MCN_INSTANCES 4 467 #define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \ 468 (n * MCN_ADDRESS_SPACE_SIZE) + \ 469 MCN_PMU_OFFSET) 470 #define MCN_MPAM_NS_OFFSET 0x000D0000 471 #define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET) 472 #define MCN_MPAM_S_OFFSET 0x000D4000 473 #define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET) 474 #define MPAM_SLCCFG_CTL_OFFSET 0x00003018 475 #define SLC_RDALLOCMODE_SHIFT 8 476 #define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT) 477 #define SLC_WRALLOCMODE_SHIFT 12 478 #define SLC_WRALLOCMODE_MASK (3 << SLC_WRALLOCMODE_SHIFT) 479 480 #define SLC_DONT_ALLOC 0 481 #define SLC_ALWAYS_ALLOC 1 482 #define SLC_ALLOC_BUS_SIGNAL_ATTR 2 483 484 #define MCN_CONFIG_OFFSET 0x204 485 #define MCN_CONFIG_ADDR (MCN_BASE_ADDR + MCN_CONFIG_OFFSET) 486 #define MCN_CONFIG_SLC_PRESENT_BIT 3 487 488 /* 489 * TC3 CPUs have the same definitions for: 490 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1 491 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1_EXTLLC_BIT 492 * Define the common macros for easier using. 493 */ 494 #define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1 495 #define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT 496 #endif /* TARGET_PLATFORM == 3 */ 497 498 #define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12) 499 500 #endif /* PLATFORM_DEF_H */ 501