1 /* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <cortex_a520.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/board_css_def.h> 14 #include <plat/arm/board/common/v2m_def.h> 15 16 /* 17 * arm_def.h depends on the platform system counter macros, so must define the 18 * platform macros before including arm_def.h. 19 */ 20 #if TARGET_PLATFORM == 4 21 #ifdef ARM_SYS_CNTCTL_BASE 22 #error "error: ARM_SYS_CNTCTL_BASE is defined prior to the PLAT_ARM_SYS_CNTCTL_BASE definition" 23 #endif 24 #define PLAT_ARM_SYS_CNTCTL_BASE UL(0x47000000) 25 #define PLAT_ARM_SYS_CNTREAD_BASE UL(0x47010000) 26 #endif 27 28 #include <plat/arm/common/arm_def.h> 29 30 #include <plat/arm/common/arm_spm_def.h> 31 #include <plat/arm/css/common/css_def.h> 32 #include <plat/arm/soc/common/soc_css_def.h> 33 #include <plat/common/common_def.h> 34 35 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 36 37 #if TRANSFER_LIST 38 /* 39 * Summation of data size of all Transfer Entries included in the Transfer list. 40 * Note: Update this field whenever new Transfer Entries are added in future. 41 */ 42 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x9000) 43 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 44 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 45 46 /* Mappings for Secure and Non-secure Transfer_list */ 47 #define TC_MAP_EL3_FW_HANDOFF MAP_REGION_FLAT( \ 48 PLAT_ARM_EL3_FW_HANDOFF_BASE, \ 49 PLAT_ARM_FW_HANDOFF_SIZE, \ 50 MT_MEMORY | MT_RW | EL3_PAS) 51 #endif /* TRANSFER_LIST */ 52 53 /* 54 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 55 * its base is ARM_AP_TZC_DRAM1_BASE. 56 * 57 * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: 58 * - BL32_BASE when SPD_spmd is enabled 59 * - Region to load secure partitions 60 * 61 * 62 * 0x8000_0000 ------------------ TC_NS_DRAM1_BASE 63 * | DTB | 64 * | (32K) | 65 * 0x8000_8000 ------------------ 66 * | NT_FW_CONFIG | 67 * | (4KB) | 68 * 0x8000_9000 ------------------ 69 * | ... | 70 * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE 71 * | OP-TEE shmem | 72 * | (2MB) | 73 * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE 74 * | | 75 * | SPMC | 76 * | SP | 77 * | (96MB) | 78 * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE 79 * | AP | 80 * | EL3 Monitor | 81 * | SCP | 82 * | (16MB) | 83 * 0xFFFF_FFFF ------------------ 84 * 85 * 86 */ 87 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 88 TC_TZC_DRAM1_SIZE) 89 #define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */ 90 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 91 TC_TZC_DRAM1_SIZE - 1) 92 93 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 94 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 95 ARM_TZC_DRAM1_SIZE - \ 96 TC_TZC_DRAM1_SIZE) 97 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1) 98 99 #define TC_NS_OPTEE_SIZE (2 * SZ_1M) 100 #define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE) 101 102 /* 103 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 104 */ 105 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 106 TC_NS_DRAM1_BASE, \ 107 TC_NS_DRAM1_SIZE, \ 108 MT_MEMORY | MT_RW | MT_NS) 109 110 111 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 112 TC_TZC_DRAM1_BASE, \ 113 TC_TZC_DRAM1_SIZE, \ 114 MT_MEMORY | MT_RW | MT_SECURE) 115 116 #define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE 117 #define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000) 118 119 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 120 PLAT_HW_CONFIG_DTB_BASE, \ 121 PLAT_ARM_HW_CONFIG_SIZE, \ 122 MT_MEMORY | MT_RO | MT_NS) 123 /* 124 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 125 * max size of BL32 image. 126 */ 127 #if defined(SPD_spmd) 128 #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) 129 130 #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR 131 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 132 #endif 133 134 /* 135 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 136 * plat_arm_mmap array defined for each BL stage. 137 */ 138 #if defined(IMAGE_BL31) 139 # if SPM_MM 140 # define PLAT_ARM_MMAP_ENTRIES 9 141 # define MAX_XLAT_TABLES 7 142 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 143 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 144 # else 145 # define PLAT_ARM_MMAP_ENTRIES 8 146 # define MAX_XLAT_TABLES 8 147 # endif 148 #elif defined(IMAGE_BL32) 149 # define PLAT_ARM_MMAP_ENTRIES 8 150 # define MAX_XLAT_TABLES 5 151 #elif !USE_ROMLIB 152 # define PLAT_ARM_MMAP_ENTRIES 11 153 # define MAX_XLAT_TABLES 7 154 #else 155 # define PLAT_ARM_MMAP_ENTRIES 12 156 # define MAX_XLAT_TABLES 6 157 #endif 158 159 /* 160 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 161 * plus a little space for growth. 162 */ 163 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 164 165 /* 166 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 167 */ 168 169 #if USE_ROMLIB 170 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 171 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 172 #else 173 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 174 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 175 #endif 176 177 /* 178 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 179 * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT 180 * and MEASURED_BOOT is enabled. 181 */ 182 # define PLAT_ARM_MAX_BL2_SIZE 0x29000 183 184 185 /* 186 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 187 * calculated using the current BL31 PROGBITS debug size plus the sizes of 188 * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and 189 * MEASURED_BOOT is enabled. 190 */ 191 #define PLAT_ARM_MAX_BL31_SIZE 0x60000 192 193 /* 194 * Size of cacheable stacks 195 */ 196 #if defined(IMAGE_BL1) 197 # define PLATFORM_STACK_SIZE 0x1000 198 #elif defined(IMAGE_BL2) 199 # define PLATFORM_STACK_SIZE 0x1000 200 #elif defined(IMAGE_BL2U) 201 # define PLATFORM_STACK_SIZE 0x400 202 #elif defined(IMAGE_BL31) 203 # if SPM_MM 204 # define PLATFORM_STACK_SIZE 0x500 205 # else 206 # define PLATFORM_STACK_SIZE 0xb00 207 # endif 208 #elif defined(IMAGE_BL32) 209 # define PLATFORM_STACK_SIZE 0x440 210 #endif 211 212 /* 213 * In the current implementation the RoT Service request that requires the 214 * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 215 * maximum required buffer size is calculated based on the platform-specific 216 * needs of this request. 217 */ 218 #define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE 0x500 219 220 #define TC_DEVICE_BASE 0x21000000 221 #define TC_DEVICE_SIZE 0x5f000000 222 223 #if defined(TARGET_FLAVOUR_FPGA) 224 #undef V2M_FLASH0_BASE 225 #undef V2M_FLASH0_SIZE 226 #if TC_FPGA_FIP_IMG_IN_RAM 227 /* 228 * Note that this is just used for the FIP, which is not required 229 * anymore once Linux has commenced booting. So we are safe allowing 230 * Linux to also make use of this memory and it doesn't need to be 231 * carved out of the devicetree. 232 * 233 * This only needs to match the RAM load address that we give the FIP 234 * on either the FPGA or FVP command line so there is no need to link 235 * it to say halfway through the RAM or anything like that. 236 */ 237 #define V2M_FLASH0_BASE UL(0xB0000000) 238 #else 239 #define V2M_FLASH0_BASE UL(0x0C000000) 240 #endif 241 #define V2M_FLASH0_SIZE UL(0x02000000) 242 #endif 243 244 // TC_MAP_DEVICE covers different peripherals 245 // available to the platform 246 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 247 TC_DEVICE_BASE, \ 248 TC_DEVICE_SIZE, \ 249 MT_DEVICE | MT_RW | MT_SECURE) 250 251 252 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 253 V2M_FLASH0_SIZE, \ 254 MT_DEVICE | MT_RO | MT_SECURE) 255 #if TARGET_PLATFORM == 2 256 #define PLAT_ARM_NSTIMER_FRAME_ID U(0) 257 #else 258 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 259 #endif 260 261 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 262 263 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 264 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 265 266 #define PLAT_ARM_NSRAM_BASE 0x06000000 267 #if TARGET_FLAVOUR_FVP 268 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 269 #else /* TARGET_FLAVOUR_FPGA */ 270 #define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */ 271 #endif /* TARGET_FLAVOUR_FPGA */ 272 273 #if TARGET_PLATFORM <= 2 274 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 275 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 276 #elif TARGET_PLATFORM >= 3 277 278 #if TC_FPGA_FS_IMG_IN_RAM 279 /* 10GB reserved for system+userdata+vendor images */ 280 #define SYSTEM_IMAGE_SIZE 0xC0000000 /* 3GB */ 281 #define USERDATA_IMAGE_SIZE 0x140000000 /* 5GB */ 282 #define VENDOR_IMAGE_SIZE 0x20000000 /* 512MB */ 283 #define RESERVE_IMAGE_SIZE 0x60000000 /* 1.5GB */ 284 #define ANDROID_FS_SIZE (SYSTEM_IMAGE_SIZE + \ 285 USERDATA_IMAGE_SIZE + \ 286 VENDOR_IMAGE_SIZE + RESERVE_IMAGE_SIZE) 287 288 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) + ANDROID_FS_SIZE 289 #define PLAT_ARM_DRAM2_SIZE ULL(0x380000000) - ANDROID_FS_SIZE 290 #else 291 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 292 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 293 #endif /* TC_FPGA_FS_IMG_IN_RAM */ 294 295 #endif /* TARGET_VERSION >= 3 */ 296 297 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) 298 299 #define TC_NS_MTE_SIZE (256 * SZ_1M) 300 /* the SCP puts the carveout at the end of DRAM2 */ 301 #define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE) 302 303 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) 304 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ 305 INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ 306 GIC_HIGHEST_SEC_PRIORITY, grp, \ 307 GIC_INTR_CFG_LEVEL) 308 309 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 310 PLAT_SP_IMAGE_NS_BUF_SIZE) 311 312 #define PLAT_ARM_SP_MAX_SIZE U(0x2000000) 313 314 /******************************************************************************* 315 * Memprotect definitions 316 ******************************************************************************/ 317 /* PSCI memory protect definitions: 318 * This variable is stored in a non-secure flash because some ARM reference 319 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 320 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 321 */ 322 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 323 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 324 325 /* Secure Watchdog Constants */ 326 #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) 327 #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) 328 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 329 #define SBSA_SECURE_WDOG_INTID 86 330 331 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 332 333 /* Index of SDS region used in the communication with SCP */ 334 #define SDS_SCP_AP_REGION_ID U(0) 335 /* Index of SDS region used in the communication with RSE */ 336 #define SDS_RSE_AP_REGION_ID U(1) 337 /* 338 * Memory region for RSE's shared data storage (SDS) 339 * It is placed right after the SCMI payload area. 340 */ 341 #define PLAT_ARM_RSE_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \ 342 CSS_SCMI_PAYLOAD_SIZE_MAX) 343 344 #define PLAT_ARM_CLUSTER_COUNT U(1) 345 #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 346 #define PLAT_MAX_CPUS_PER_CLUSTER U(14) 347 #else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 348 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 349 #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 350 #define PLAT_MAX_PE_PER_CPU U(1) 351 352 #define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT) 353 354 /* Message Handling Unit (MHU) base addresses */ 355 #if TARGET_PLATFORM <= 2 356 #define PLAT_CSS_MHU_BASE UL(0x45400000) 357 #elif TARGET_PLATFORM >= 3 358 #define PLAT_CSS_MHU_BASE UL(0x46000000) 359 #endif /* TARGET_PLATFORM >= 3 */ 360 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 361 362 /* AP<->RSS MHUs */ 363 #if TARGET_PLATFORM <= 2 364 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000) 365 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000) 366 #elif TARGET_PLATFORM == 3 367 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) 368 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000) 369 #elif TARGET_PLATFORM == 4 370 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) 371 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49010000) 372 #endif 373 374 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 375 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 376 377 /* 378 * Physical and virtual address space limits for MMU in AARCH64 379 */ 380 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 381 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 382 383 /* GIC related constants */ 384 #define PLAT_ARM_GICD_BASE UL(0x30000000) 385 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 386 #define PLAT_ARM_GICR_BASE UL(0x30080000) 387 388 /* 389 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 390 * SCP_BL2 size plus a little space for growth. 391 */ 392 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x30000 393 394 /* 395 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 396 * SCP_BL2U size plus a little space for growth. 397 */ 398 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x30000 399 400 #if TARGET_PLATFORM <= 2 401 /* TZC Related Constants */ 402 #define PLAT_ARM_TZC_BASE UL(0x25000000) 403 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 404 405 #define TZC400_OFFSET UL(0x1000000) 406 #define TZC400_COUNT 4 407 408 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 409 (n * TZC400_OFFSET)) 410 411 #define TZC_NSAID_DEFAULT U(0) 412 413 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 414 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 415 416 /* 417 * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to 418 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as 419 * secure. The second and third regions gives non secure access to rest of DRAM. 420 */ 421 #define TC_TZC_REGIONS_DEF \ 422 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 423 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 424 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 425 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 426 {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ 427 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 428 #endif 429 430 /* virtual address used by dynamic mem_protect for chunk_base */ 431 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 432 433 #if ARM_GPT_SUPPORT 434 /* 435 * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. 436 * Offset of the FIP in the GPT image. BL1 component uses this option 437 * as it does not load the partition table to get the FIP base 438 * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) 439 * (i.e. after reserved sectors 0-47). 440 * Offset = 48 * 512 = 0x6000 441 */ 442 #undef PLAT_ARM_FIP_OFFSET_IN_GPT 443 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 444 #endif /* ARM_GPT_SUPPORT */ 445 446 /* UART related constants */ 447 448 #define TC_UART0 0x2a400000 449 #define TC_UART1 0x2a410000 450 451 /* 452 * TODO: if any more undefs are needed, it's better to consider dropping the 453 * board_css_def.h include above 454 */ 455 #undef PLAT_ARM_BOOT_UART_BASE 456 #undef PLAT_ARM_RUN_UART_BASE 457 458 #undef PLAT_ARM_CRASH_UART_BASE 459 #undef PLAT_ARM_BOOT_UART_CLK_IN_HZ 460 #undef PLAT_ARM_RUN_UART_CLK_IN_HZ 461 462 #undef ARM_CONSOLE_BAUDRATE 463 #define ARM_CONSOLE_BAUDRATE 38400 464 465 #if TARGET_PLATFORM <= 2 466 #define TC_UARTCLK 5000000 467 #elif TARGET_PLATFORM == 3 468 #define TC_UARTCLK 3750000 469 #elif TARGET_PLATFORM == 4 470 #define TC_UARTCLK 4000000 471 #endif /* TARGET_PLATFORM <=2 */ 472 473 474 #if TARGET_FLAVOUR_FVP 475 #define PLAT_ARM_BOOT_UART_BASE TC_UART1 476 #else /* TARGET_FLAVOUR_FPGA */ 477 #define PLAT_ARM_BOOT_UART_BASE TC_UART0 478 #endif /* TARGET_FLAVOUR_FPGA */ 479 480 #define PLAT_ARM_RUN_UART_BASE TC_UART0 481 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 482 483 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK 484 #define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK 485 486 #if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) 487 #define NCI_BASE_ADDR UL(0x4F000000) 488 #if (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA) 489 #define MCN_ADDRESS_SPACE_SIZE 0x00120000 490 #else 491 #define MCN_ADDRESS_SPACE_SIZE 0x00130000 492 #endif /* (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA) */ 493 #if TARGET_PLATFORM == 3 494 #define MCN_OFFSET_IN_NCI 0x00C90000 495 #else /* TARGET_PLATFORM == 4 */ 496 #ifdef TARGET_FLAVOUR_FPGA 497 #define MCN_OFFSET_IN_NCI 0x00420000 498 #else 499 #define MCN_OFFSET_IN_NCI 0x00D80000 500 #endif /* TARGET_FLAVOUR_FPGA */ 501 #endif /* TARGET_PLATFORM == 3 */ 502 #define MCN_BASE_ADDR(n) (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI + \ 503 ((n) * MCN_ADDRESS_SPACE_SIZE)) 504 #define MCN_PMU_OFFSET 0x000C4000 505 #define MCN_MICROARCH_OFFSET 0x000E4000 506 #define MCN_MICROARCH_BASE_ADDR(n) (MCN_BASE_ADDR(n) + \ 507 MCN_MICROARCH_OFFSET) 508 #define MCN_SCR_OFFSET 0x4 509 #define MCN_SCR_PMU_BIT 10 510 #if TARGET_PLATFORM == 3 511 #define MCN_INSTANCES 4 512 #else /* TARGET_PLATFORM == 4 */ 513 #define MCN_INSTANCES 8 514 #endif /* TARGET_PLATFORM == 3 */ 515 #define MCN_PMU_ADDR(n) (MCN_BASE_ADDR(n) + \ 516 MCN_PMU_OFFSET) 517 #define MCN_MPAM_NS_OFFSET 0x000D0000 518 #define MCN_MPAM_NS_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_NS_OFFSET) 519 #define MCN_MPAM_S_OFFSET 0x000D4000 520 #define MCN_MPAM_S_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_S_OFFSET) 521 #define MPAM_SLCCFG_CTL_OFFSET 0x00003018 522 #define SLC_RDALLOCMODE_SHIFT 8 523 #define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT) 524 #define SLC_WRALLOCMODE_SHIFT 12 525 #define SLC_WRALLOCMODE_MASK (3 << SLC_WRALLOCMODE_SHIFT) 526 527 #define SLC_DONT_ALLOC 0 528 #define SLC_ALWAYS_ALLOC 1 529 #define SLC_ALLOC_BUS_SIGNAL_ATTR 2 530 531 #define MCN_CONFIG_OFFSET 0x204 532 #define MCN_CONFIG_ADDR(n) (MCN_BASE_ADDR(n) + MCN_CONFIG_OFFSET) 533 #define MCN_CONFIG_SLC_PRESENT_BIT 3 534 535 /* 536 * TC3 CPUs have the same definitions for: 537 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1 538 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1_EXTLLC_BIT 539 * Define the common macros for easier using. 540 */ 541 #define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1 542 #define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT 543 #endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ 544 545 #define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12) 546 547 #endif /* PLATFORM_DEF_H */ 548