feat(locks): add non-blocking spinlock_try() API

Add a non-blocking `spin_trylock()` function to the existing spinlock
implementation. This API attempts to acquire the lock and returns `1`
on succes

feat(locks): add non-blocking spinlock_try() API

Add a non-blocking `spin_trylock()` function to the existing spinlock
implementation. This API attempts to acquire the lock and returns `1`
on success or `0` if the lock is already held. It enables conditional
locking scenarios where blocking is undesirable.

Change-Id: I9483206952d1a34dc245ebf69e80c3645b658946
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(psci): add API to get number of CPUs currently in ON state" into integration

Merge "fix(rme): enable support for FEAT_D128 on Realm world" into integration

Merge "fix(libc): add missing curly braces" into integration

fix(rme): enable support for FEAT_D128 on Realm world

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I9a4431038968a260e1a4998d8a4f84a07768db74

feat(errata): implement workaround for DSU-120 erratum 2900952

DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum

feat(errata): implement workaround for DSU-120 erratum 2900952

DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum is fixed in certain implementations of r2p0 which can be
determined by reading the IMP_CLUSTERREVIDR_EL1[1] register field
where a set bit indicates that the erratum is fixed in this part.

The workaround is to set the CLUSTERACTLR_EL1 bits [21:20] to 0x3
which ignores CBusy from the system interconnect and
setting CLUSTERACTLR_EL1 bit [8] to 1 to assert CBusy from DSU to
all the cores when DSU is busy.

SDEN: https://developer.arm.com/documentation/SDEN-2453103/1200/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I87aa440ab5c35121aff703032f5cf7a62d0b0bb4

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feat(psci): add API to get number of CPUs currently in ON state

Introduce a new PSCI helper function `psci_num_cpus_running_on_safe()`
to return the number of CPUs that are currently in the ON state

feat(psci): add API to get number of CPUs currently in ON state

Introduce a new PSCI helper function `psci_num_cpus_running_on_safe()`
to return the number of CPUs that are currently in the ON state.
This API locks the PSCI power state data to ensure consistency and
is safe to call in concurrent environments.

This utility can assist components that need to reason about system
CPU activity or coordinate operations based on active CPUs.

Change-Id: Ie15aa4bd393a5f01e7cd80ae8a9b28707fde7c53
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 1917258

Cortex-A710 erratum 1917258 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4

fix(cpus): workaround for Cortex-A710 erratum 1917258

Cortex-A710 erratum 1917258 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[43]. This has no
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I1fae91a5e3a8ecea255f0f0a481bfd6196a7db51
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 1916945

Cortex-A710 erratum 1916945 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_

fix(cpus): workaround for Cortex-A710 erratum 1916945

Cortex-A710 erratum 1916945 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[8]. This has a slight
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I54793492c527928d7f266165a31b8613de838e69
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15].

fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15]. This has a slight
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I703f0e6ee122e44a9bc284d90f1465039e3b40e4
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "fix(errata): keep leading zeros in CVE ID prints" into integration

refactor(fconf): use macro to set image info

Use the provided macro to set the image_info_t header rather than doing
it manually.

Change-Id: I45fd62c3947c9a23c2cb0df542ce2424955e2f8b
Signed-off-by:

refactor(fconf): use macro to set image info

Use the provided macro to set the image_info_t header rather than doing
it manually.

Change-Id: I45fd62c3947c9a23c2cb0df542ce2424955e2f8b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "fix(libc): add const qualifier" into integration

fix(cpus): drop esb from the Neoverse N1

An esb is only necessary when FEAT_IESB is not present in hardware but
FEAT_RAS is. When FEAT_RAS is present we rely on the fact that FEAT_IESB
will also be

fix(cpus): drop esb from the Neoverse N1

An esb is only necessary when FEAT_IESB is not present in hardware but
FEAT_RAS is. When FEAT_RAS is present we rely on the fact that FEAT_IESB
will also be present and an implicit esb will pre present on eret.

Well the N1 implements FEAT_RAS and FEAT_IESB and the platforms that use
it (n1sdp) enable the features in firmware. So the esb is redundant.
There are dynamic platforms where this may not necessarily be true,
however, the esb is in an erratum workaround which cannot be present in
these platforms.

Change-Id: I5775180ec61373cc5d1b9831e3fa0f2fbb19eab9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(errata): keep leading zeros in CVE ID prints

The errata printing function would drop leading zeros on CVE
numbers so this updates the format string to make sure they are
printed. This is to conf

fix(errata): keep leading zeros in CVE ID prints

The errata printing function would drop leading zeros on CVE
numbers so this updates the format string to make sure they are
printed. This is to conform to the CVE naming convention where
ID numbers of less than 4 digits are prepended with 0s up to 4
digits.

This also updates a confusing comment indicating that leading
zeros could be used to work around a potential issue if CVE and
erratum IDs clash. Values with leading zeros will be interpreted
as octal numbers which is not desirable behavior so this should
not be recommended. Realistically, a CVE ID and erratum ID being
the same is *extremely* unlikely since CVE ID start over each
year and are 4-5 digits for Arm, and Errata IDs are 6-7 digits.

Change-Id: Idf2be50cea6828a3d30c6e58fda477ec1398bc7c
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "feat(spe): add support for FEAT_SPE_FDS" into integration

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY
feat(cpufeat): add support for PMUv3p9

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Merge "feat(cpufeat): add support for FEAT_PAUTH_LR" into integration

Merge "fix(libc): typecast expressions to match data type" into integration

Merge changes I005586ef,I0d4d74bc into integration

* changes:
fix(cpufeat): replace "bti" mnemonic with hint instructions
fix(cpufeat): improve xpaci wrapper

fix(cpufeat): replace "bti" mnemonic with hint instructions

Older GNU binutils version require to specify at least "armv8.5-a" for
the ARM architecture revision to accept "bti" instructions in the
a

fix(cpufeat): replace "bti" mnemonic with hint instructions

Older GNU binutils version require to specify at least "armv8.5-a" for
the ARM architecture revision to accept "bti" instructions in the
assembly code. Binutils v2.35 have relaxed this, since "bti" is in the
hint space, so is ignored on older cores and does NOT require a BTI
enabled core to execute.

To not exclude those older binutils versions (as shipped with Ubuntu
20.04), use the "hint" encoding for the "bti" instructions, which are
accepted regardless of the minimum architecture revision. Hide this
encoding in a macro, to make the "bti" usage more readable in the
source code.

Change-Id: I005586efd8974a3f2c7202896c881bb5fed07eea
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by

feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by: James Clark <james.clark2@arm.com>

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feat(cpufeat): add support for FEAT_PAUTH_LR

This patch enables FEAT_PAUTH_LR at EL3 on systems that support it when
the new ENABLE_FEAT_PAUTH_LR flag is set.

Currently, PAUTH_LR is only supported

feat(cpufeat): add support for FEAT_PAUTH_LR

This patch enables FEAT_PAUTH_LR at EL3 on systems that support it when
the new ENABLE_FEAT_PAUTH_LR flag is set.

Currently, PAUTH_LR is only supported by arm clang compiler and not GCC.

Change-Id: I7db1e34b661ed95cad75850b62878ac5d98466ea
Signed-off-by: John Powell <john.powell@arm.com>

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refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* cal

refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* calls.

Previously, EXTRA functions were individually implemented for
each SMCCC_ARCH_WORKAROUND_*, an approach that becomes unmanageable
with the increasing number of workarounds.
By looking up erratum entries for CVE check, the process is streamlined,
reducing overhead associated with creating and
maintaining EXTRA functions for each new workaround.

New Errata entries are created for SMC workarounds and
that is used to target cpus that are uniquely impacted
by SMC workarounds.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I873534e367a35c99461d0a616ff7bf856a0000af

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refactor(cpus): move errata check to common code

This patch centralizes some of the Errata ABI code
that could be used for checking if an Errata has been applied
to cpu library since the function is

refactor(cpus): move errata check to common code

This patch centralizes some of the Errata ABI code
that could be used for checking if an Errata has been applied
to cpu library since the function is mostly generic.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2c6d4468f7125d4d99ccdebc5ea8f9e4390360cc

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