1 /* 2 * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <common/debug.h> 11 #include <common/ep_info.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 #include <plat_arm.h> 18 #include <plat_fdt.h> 19 20 #include "def.h" 21 #include <ipi.h> 22 #include <plat_private.h> 23 #include "pm_api_sys.h" 24 #include "pm_client.h" 25 #include <pm_common.h> 26 #include "pm_defs.h" 27 #include "pm_svc_main.h" 28 29 static uintptr_t sec_entry; 30 31 static int32_t versal2_pwr_domain_on(u_register_t mpidr) 32 { 33 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 34 int32_t ret = (int32_t) PSCI_E_INTERN_FAIL; 35 enum pm_ret_status pm_ret; 36 const struct pm_proc *proc; 37 38 if (cpu_id != -1) { 39 proc = pm_get_proc((uint32_t)cpu_id); 40 if (proc != NULL) { 41 pm_ret = pm_req_wakeup(proc->node_id, 42 (uint32_t) 43 ((sec_entry & 0xFFFFFFFFU) | 0x1U), 44 sec_entry >> 32, 0, 0); 45 46 if (pm_ret == PM_RET_SUCCESS) { 47 /* Clear power down request */ 48 pm_client_wakeup(proc); 49 ret = (int32_t) PSCI_E_SUCCESS; 50 } 51 } 52 } 53 54 return ret; 55 } 56 57 /** 58 * versal2_pwr_domain_off() - Turn off core. 59 * @target_state: Targeted state. 60 */ 61 static void versal2_pwr_domain_off(const psci_power_state_t *target_state) 62 { 63 const struct pm_proc *proc; 64 uint32_t cpu_id = plat_my_core_pos(); 65 enum pm_ret_status pm_ret; 66 size_t i; 67 68 proc = pm_get_proc(cpu_id); 69 if (proc == NULL) { 70 ERROR("Failed to get proc %d\n", cpu_id); 71 goto err; 72 } 73 74 for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 75 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 76 __func__, i, target_state->pwr_domain_state[i]); 77 } 78 79 plat_gic_cpuif_disable(); 80 /* 81 * Send request to PMC to power down the appropriate APU CPU 82 * core. 83 * According to PSCI specification, CPU_off function does not 84 * have resume address and CPU core can only be woken up 85 * invoking CPU_on function, during which resume address will 86 * be set. 87 */ 88 pm_ret = pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0, 89 NON_SECURE); 90 91 if (pm_ret != PM_RET_SUCCESS) { 92 ERROR("Failed to power down CPU %d\n", cpu_id); 93 } 94 err: 95 return; 96 } 97 98 /** 99 * versal2_system_reset() - Send the reset request to firmware for the 100 * system to reset. This function does not 101 * return as it resets system. 102 */ 103 static void __dead2 versal2_system_reset(void) 104 { 105 uint32_t timeout = 10000U; 106 enum pm_ret_status pm_ret; 107 int32_t ret; 108 109 request_cpu_pwrdwn(); 110 111 /* 112 * Send the system reset request to the firmware if power down request 113 * is not received from firmware. 114 */ 115 if (pm_pwrdwn_req_status() == false) { 116 /* 117 * TODO: shutdown scope for this reset needs be revised once 118 * we have a clearer understanding of the overall reset scoping 119 * including the implementation of SYSTEM_RESET2. 120 */ 121 pm_ret = pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, 122 pm_get_shutdown_scope(), NON_SECURE); 123 124 if (pm_ret != PM_RET_SUCCESS) { 125 WARN("System shutdown failed\n"); 126 } 127 128 /* 129 * Wait for system shutdown request completed and idle callback 130 * not received. 131 */ 132 do { 133 ret = ipi_mb_enquire_status(primary_proc->ipi->local_ipi_id, 134 primary_proc->ipi->remote_ipi_id); 135 udelay(100); 136 timeout--; 137 } while ((ret != (int32_t)IPI_MB_STATUS_RECV_PENDING) && (timeout > 0U)); 138 } 139 140 (void)psci_cpu_off(); 141 142 while (true) { 143 wfi(); 144 } 145 } 146 147 /** 148 * versal2_pwr_domain_suspend() - Send request to PMC to suspend core. 149 * @target_state: Targeted state. 150 */ 151 static void versal2_pwr_domain_suspend(const psci_power_state_t *target_state) 152 { 153 const struct pm_proc *proc; 154 uint32_t cpu_id = plat_my_core_pos(); 155 uint32_t state; 156 enum pm_ret_status ret; 157 size_t i; 158 159 proc = pm_get_proc(cpu_id); 160 if (proc == NULL) { 161 ERROR("Failed to get proc %d\n", cpu_id); 162 goto err; 163 } 164 165 for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 166 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 167 __func__, i, target_state->pwr_domain_state[i]); 168 } 169 170 plat_gic_cpuif_disable(); 171 172 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 173 plat_gic_save(); 174 } 175 176 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? 177 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 178 179 /* Send request to PMC to suspend this core */ 180 ret = pm_self_suspend(proc->node_id, MAX_LATENCY, state, sec_entry, 181 NON_SECURE); 182 183 if (ret != PM_RET_SUCCESS) { 184 ERROR("Failed to power down CPU %d\n", cpu_id); 185 } 186 187 err: 188 return; 189 } 190 191 static int32_t versal2_validate_ns_entrypoint(uint64_t ns_entrypoint) 192 { 193 int32_t ret = PSCI_E_SUCCESS; 194 struct reserve_mem_range *rmr; 195 uint32_t index = 0, counter = 0; 196 197 rmr = get_reserved_entries_fdt(&counter); 198 199 VERBOSE("Validate ns_entry point %lx\n", ns_entrypoint); 200 201 if (counter != 0) { 202 while (index < counter) { 203 if ((ns_entrypoint >= rmr[index].base) && 204 (ns_entrypoint <= rmr[index].size)) { 205 ret = PSCI_E_INVALID_ADDRESS; 206 break; 207 } 208 index++; 209 } 210 } else { 211 if ((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT)) { 212 ret = PSCI_E_INVALID_ADDRESS; 213 } 214 } 215 216 return ret; 217 } 218 219 static void versal2_pwr_domain_on_finish(const psci_power_state_t *target_state) 220 { 221 (void)target_state; 222 223 /* Enable the gic cpu interface */ 224 plat_gic_pcpu_init(); 225 226 /* Program the gic per-cpu distributor or re-distributor interface */ 227 plat_gic_cpuif_enable(); 228 } 229 230 /** 231 * versal2_pwr_domain_suspend_finish() - Performs actions to finish 232 * suspend procedure. 233 * @target_state: Targeted state. 234 */ 235 static void versal2_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 236 { 237 const struct pm_proc *proc; 238 uint32_t cpu_id = plat_my_core_pos(); 239 size_t i; 240 241 proc = pm_get_proc(cpu_id); 242 if (proc == NULL) { 243 ERROR("Failed to get proc %d\n", cpu_id); 244 goto err; 245 } 246 247 for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 248 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 249 __func__, i, target_state->pwr_domain_state[i]); 250 } 251 252 /* Clear the APU power control register for this cpu */ 253 pm_client_wakeup(proc); 254 255 /* APU was turned off, so restore GIC context */ 256 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 257 plat_gic_resume(); 258 } 259 260 plat_gic_cpuif_enable(); 261 262 err: 263 return; 264 } 265 266 /** 267 * versal2_system_off() - Send the system off request to firmware. 268 * This function does not return as it puts core into WFI 269 */ 270 static void __dead2 versal2_system_off(void) 271 { 272 enum pm_ret_status ret; 273 274 /* Send the power down request to the PMC */ 275 ret = pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, 276 pm_get_shutdown_scope(), NON_SECURE); 277 278 if (ret != PM_RET_SUCCESS) { 279 ERROR("System shutdown failed\n"); 280 } 281 282 while (true) { 283 wfi(); 284 } 285 } 286 287 /** 288 * versal2_validate_power_state() - Ensure that the power state 289 * parameter in request is valid. 290 * @power_state: Power state of core. 291 * @req_state: Requested state. 292 * 293 * Return: Returns status, either PSCI_E_SUCCESS or reason. 294 */ 295 static int32_t versal2_validate_power_state(unsigned int power_state, 296 psci_power_state_t *req_state) 297 { 298 uint32_t pstate = psci_get_pstate_type(power_state); 299 int32_t ret = PSCI_E_SUCCESS; 300 301 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 302 303 assert(req_state); 304 305 /* Sanity check the requested state */ 306 if (pstate == PSTATE_TYPE_STANDBY) { 307 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 308 } else { 309 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 310 } 311 312 /* The 'state_id' is expected to be zero */ 313 if (psci_get_pstate_id(power_state) != 0U) { 314 ret = PSCI_E_INVALID_PARAMS; 315 } 316 317 return ret; 318 } 319 320 /** 321 * versal2_get_sys_suspend_power_state() - Get power state for system 322 * suspend. 323 * @req_state: Requested state. 324 */ 325 static void versal2_get_sys_suspend_power_state(psci_power_state_t *req_state) 326 { 327 uint64_t i; 328 329 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { 330 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 331 } 332 } 333 334 /** 335 * Export the platform specific power ops. 336 */ 337 static const struct plat_psci_ops versal2_nopmc_psci_ops = { 338 .pwr_domain_on = versal2_pwr_domain_on, 339 .pwr_domain_off = versal2_pwr_domain_off, 340 .pwr_domain_on_finish = versal2_pwr_domain_on_finish, 341 .pwr_domain_suspend = versal2_pwr_domain_suspend, 342 .pwr_domain_suspend_finish = versal2_pwr_domain_suspend_finish, 343 .system_off = versal2_system_off, 344 .system_reset = versal2_system_reset, 345 .validate_ns_entrypoint = versal2_validate_ns_entrypoint, 346 .validate_power_state = versal2_validate_power_state, 347 .get_sys_suspend_power_state = versal2_get_sys_suspend_power_state, 348 }; 349 350 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 351 const struct plat_psci_ops **psci_ops) 352 { 353 sec_entry = sec_entrypoint; 354 355 VERBOSE("Setting up entry point %lx\n", sec_entry); 356 357 *psci_ops = &versal2_nopmc_psci_ops; 358 359 return 0; 360 } 361 362 int32_t sip_svc_setup_init(void) 363 { 364 return pm_setup(); 365 } 366 367 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 368 const void *cookie, void *handle, uint64_t flags) 369 { 370 return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 371 } 372