1 /* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <common/debug.h> 11 #include <common/ep_info.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/common/platform.h> 16 #include <plat_arm.h> 17 18 #include "drivers/delay_timer.h" 19 #include <plat_private.h> 20 #include "pm_api_sys.h" 21 #include "pm_client.h" 22 #include <pm_common.h> 23 #include "pm_ipi.h" 24 #include "pm_svc_main.h" 25 26 #define SEC_ENTRY_ADDRESS_MASK 0xFFFFFFFFUL 27 #define RESUME_ADDR_SET 0x1UL 28 29 static uintptr_t versal_sec_entry; 30 31 static int32_t versal_pwr_domain_on(u_register_t mpidr) 32 { 33 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 34 const struct pm_proc *proc; 35 int32_t ret = PSCI_E_INTERN_FAIL; 36 37 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); 38 39 if (cpu_id == -1) { 40 goto exit_label; 41 } 42 43 proc = pm_get_proc((uint32_t)cpu_id); 44 if (proc == NULL) { 45 goto exit_label; 46 } 47 48 /* Send request to PMC to wake up selected ACPU core */ 49 (void)pm_req_wakeup(proc->node_id, 50 (uint32_t)((versal_sec_entry & SEC_ENTRY_ADDRESS_MASK) | 51 RESUME_ADDR_SET), versal_sec_entry >> 32, 0, NON_SECURE); 52 53 /* Clear power down request */ 54 pm_client_wakeup(proc); 55 56 ret = PSCI_E_SUCCESS; 57 58 exit_label: 59 return ret; 60 } 61 62 /** 63 * versal_pwr_domain_suspend() - This function sends request to PMC to suspend 64 * core. 65 * @target_state: Targated state. 66 * 67 */ 68 static void versal_pwr_domain_suspend(const psci_power_state_t *target_state) 69 { 70 uint32_t state; 71 uint32_t cpu_id = plat_my_core_pos(); 72 const struct pm_proc *proc = pm_get_proc(cpu_id); 73 74 if (proc == NULL) { 75 return; 76 } 77 78 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { 79 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 80 __func__, i, target_state->pwr_domain_state[i]); 81 } 82 83 plat_versal_gic_cpuif_disable(); 84 85 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 86 plat_versal_gic_save(); 87 } 88 89 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? 90 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 91 92 /* Send request to PMC to suspend this core */ 93 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry, 94 NON_SECURE); 95 96 /* APU is to be turned off */ 97 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 98 /* disable coherency */ 99 plat_arm_interconnect_exit_coherency(); 100 } 101 } 102 103 /** 104 * versal_pwr_domain_suspend_finish() - This function performs actions to finish 105 * suspend procedure. 106 * @target_state: Targated state. 107 * 108 */ 109 static void versal_pwr_domain_suspend_finish( 110 const psci_power_state_t *target_state) 111 { 112 uint32_t cpu_id = plat_my_core_pos(); 113 const struct pm_proc *proc = pm_get_proc(cpu_id); 114 115 if (proc == NULL) { 116 return; 117 } 118 119 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { 120 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 121 __func__, i, target_state->pwr_domain_state[i]); 122 } 123 124 /* Clear the APU power control register for this cpu */ 125 pm_client_wakeup(proc); 126 127 /* enable coherency */ 128 plat_arm_interconnect_enter_coherency(); 129 130 /* APU was turned off, so restore GIC context */ 131 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 132 plat_versal_gic_resume(); 133 } 134 135 plat_versal_gic_cpuif_enable(); 136 } 137 138 static void versal_pwr_domain_on_finish(const psci_power_state_t *target_state) 139 { 140 /* 141 * Typecasting to void to intentionally retain the variable and avoid 142 * MISRA violation for unused parameters. This may be used in the 143 * future if specific action is required based on CPU power state. 144 */ 145 (void)target_state; 146 147 /* Enable the gic cpu interface */ 148 plat_versal_gic_pcpu_init(); 149 150 /* Program the gic per-cpu distributor or re-distributor interface */ 151 plat_versal_gic_cpuif_enable(); 152 } 153 154 /** 155 * versal_system_off() - This function sends the system off request to firmware. 156 * This function does not return. 157 * 158 */ 159 static void __dead2 versal_system_off(void) 160 { 161 /* Send the power down request to the PMC */ 162 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, 163 pm_get_shutdown_scope(), NON_SECURE); 164 165 while (true) { 166 wfi(); 167 } 168 } 169 170 /** 171 * versal_system_reset() - This function sends the reset request to firmware 172 * for the system to reset. This function does not 173 * return. 174 * 175 */ 176 static void __dead2 versal_system_reset(void) 177 { 178 uint32_t ret, timeout = 10000U; 179 180 request_cpu_pwrdwn(); 181 182 /* 183 * Send the system reset request to the firmware if power down request 184 * is not received from firmware. 185 */ 186 if (!pm_pwrdwn_req_status()) { 187 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, 188 pm_get_shutdown_scope(), NON_SECURE); 189 190 /* 191 * Wait for system shutdown request completed and idle callback 192 * not received. 193 */ 194 do { 195 ret = ipi_mb_enquire_status(primary_proc->ipi->local_ipi_id, 196 primary_proc->ipi->remote_ipi_id); 197 udelay(100); 198 timeout--; 199 } while ((ret != IPI_MB_STATUS_RECV_PENDING) && (timeout > 0U)); 200 } 201 202 (void)psci_cpu_off(); 203 204 while (true) { 205 wfi(); 206 } 207 } 208 209 static int32_t versal_validate_ns_entrypoint(uint64_t ns_entrypoint) 210 { 211 int32_t ret = PSCI_E_SUCCESS; 212 213 if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) || 214 ((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) { 215 ret = PSCI_E_INVALID_ADDRESS; 216 } 217 218 return ret; 219 } 220 221 /** 222 * versal_pwr_domain_off() - This function performs actions to turn off core. 223 * @target_state: Targated state. 224 * 225 */ 226 static void versal_pwr_domain_off(const psci_power_state_t *target_state) 227 { 228 uint32_t ret, fw_api_version, version_type[RET_PAYLOAD_ARG_CNT] = {0U}; 229 uint32_t cpu_id = plat_my_core_pos(); 230 const struct pm_proc *proc = pm_get_proc(cpu_id); 231 232 if (proc == NULL) { 233 return; 234 } 235 236 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { 237 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 238 __func__, i, target_state->pwr_domain_state[i]); 239 } 240 241 /* Prevent interrupts from spuriously waking up this cpu */ 242 plat_versal_gic_cpuif_disable(); 243 244 /* 245 * Send request to PMC to power down the appropriate APU CPU 246 * core. 247 * According to PSCI specification, CPU_off function does not 248 * have resume address and CPU core can only be woken up 249 * invoking CPU_on function, during which resume address will 250 * be set. 251 */ 252 ret = (uint32_t)pm_feature_check((uint32_t)PM_SELF_SUSPEND, 253 &version_type[0], NON_SECURE); 254 if (ret == (uint32_t)PM_RET_SUCCESS) { 255 fw_api_version = version_type[0] & 0xFFFFU; 256 if (fw_api_version >= 3U) { 257 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0, 258 NON_SECURE); 259 } else { 260 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0, 261 NON_SECURE); 262 } 263 } 264 } 265 266 /** 267 * versal_validate_power_state() - This function ensures that the power state 268 * parameter in request is valid. 269 * @power_state: Power state of core. 270 * @req_state: Requested state. 271 * 272 * Return: Returns status, either success or reason. 273 * 274 */ 275 static int32_t versal_validate_power_state(uint32_t power_state, 276 psci_power_state_t *req_state) 277 { 278 int32_t ret = PSCI_E_SUCCESS; 279 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 280 281 uint32_t pstate = psci_get_pstate_type(power_state); 282 283 assert(req_state != NULL); 284 285 /* Sanity check the requested state */ 286 if (pstate == PSTATE_TYPE_STANDBY) { 287 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 288 } else { 289 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 290 } 291 292 /* We expect the 'state id' to be zero */ 293 if (psci_get_pstate_id(power_state) != 0U) { 294 ret = PSCI_E_INVALID_PARAMS; 295 } 296 297 return ret; 298 } 299 300 /** 301 * versal_get_sys_suspend_power_state() - Get power state for system suspend. 302 * @req_state: Requested state. 303 * 304 */ 305 static void versal_get_sys_suspend_power_state(psci_power_state_t *req_state) 306 { 307 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 308 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 309 } 310 311 static const struct plat_psci_ops versal_nopmc_psci_ops = { 312 .pwr_domain_on = versal_pwr_domain_on, 313 .pwr_domain_off = versal_pwr_domain_off, 314 .pwr_domain_on_finish = versal_pwr_domain_on_finish, 315 .pwr_domain_suspend = versal_pwr_domain_suspend, 316 .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish, 317 .system_off = versal_system_off, 318 .system_reset = versal_system_reset, 319 .validate_ns_entrypoint = versal_validate_ns_entrypoint, 320 .validate_power_state = versal_validate_power_state, 321 .get_sys_suspend_power_state = versal_get_sys_suspend_power_state, 322 }; 323 324 /******************************************************************************* 325 * Export the platform specific power ops. 326 ******************************************************************************/ 327 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 328 const struct plat_psci_ops **psci_ops) 329 { 330 versal_sec_entry = sec_entrypoint; 331 332 *psci_ops = &versal_nopmc_psci_ops; 333 334 return 0; 335 } 336