Use PFR0 to identify need for mitigation of CVE-2017-5715

If the CSV2 field reads as 1 then branch targets trained in one
context cannot affect speculative execution in a different context.
In that

Use PFR0 to identify need for mitigation of CVE-2017-5715

If the CSV2 field reads as 1 then branch targets trained in one
context cannot affect speculative execution in a different context.
In that case skip the workaround on Cortex A72 and A73.

Change-Id: Ide24fb6efc77c548e4296295adc38dca87d042ee
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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Merge pull request #1282 from robertovargas-arm/misra-changes

Misra changes

Fix MISRA rule 8.4 Part 1

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 al

Fix MISRA rule 8.4 Part 1

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all

Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Fix MISRA rule 8.4 in common code

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined.

Change-Id: I26e042cb251a6f9590afa1340fda

Fix MISRA rule 8.4 in common code

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined.

Change-Id: I26e042cb251a6f9590afa1340fdac73e42f23979
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Fix MISRA rule 8.3 in common code

Rule 8.3: All declarations of an object or function shall
use the same names and type qualifiers.

Change-Id: Iff384187c74a598a4e73f350a1893b60e9d16cec
Si

Fix MISRA rule 8.3 in common code

Rule 8.3: All declarations of an object or function shall
use the same names and type qualifiers.

Change-Id: Iff384187c74a598a4e73f350a1893b60e9d16cec
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Merge pull request #1287 from davidcunado-arm/dc/fix_misra

Update ULL() macro and instances of ull to comply with MISRA

Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatch

Clarify comments in xlat tables lib and fixes related to the TLB

Merge pull request #1274 from dp-arm/dp/a75

AMU fixes for Cortex-A75

Update ULL() macro and instances of ull to comply with MISRA

MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes.

This patch resolves this for the ULL() macro by usin

Update ULL() macro and instances of ull to comply with MISRA

MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes.

This patch resolves this for the ULL() macro by using ULL suffix instead
of the ull suffix.

Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01
Signed-off-by: David Cunado <david.cunado@arm.com>

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Invalidate TLB entries during warm boot

During the warm boot sequence:

1. The MMU is enabled with the data cache disabled. The MMU table walker
is set up to access the translation tables as in c

Invalidate TLB entries during warm boot

During the warm boot sequence:

1. The MMU is enabled with the data cache disabled. The MMU table walker
is set up to access the translation tables as in cacheable memory,
but its accesses are non-cacheable because SCTLR_EL3.C controls them
as well.
2. The interconnect is set up and the CPU enters coherency with the
rest of the system.
3. The data cache is enabled.

If the support for dynamic translation tables is enabled and another CPU
makes changes to a region, the changes may only be present in the data
cache, not in RAM. The CPU that is booting isn't in coherency with the
rest of the system, so the table walker of that CPU isn't either. This
means that it may read old entries from RAM and it may have invalid TLB
entries corresponding to the dynamic mappings.

This is not a problem for the boot code because the mapping is 1:1 and
the regions are static. However, the code that runs after the boot
sequence may need to access the dynamically mapped regions.

This patch invalidates all TLBs during warm boot when the dynamic
translation tables support is enabled to prevent this problem.

Change-Id: I80264802dc0aa1cb3edd77d0b66b91db6961af3d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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MISRA fixes for Cortex A75 AMU implementation

Change-Id: I61c9fdfda0c0b3c3ec6249519db23602cf4c2100
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

Refactor AMU support for Cortex A75

This patch also fixes the assumption that the counters are disabled on
the resume path. This is incorrect as the AMU counters are enabled
early in the CPU reset

Refactor AMU support for Cortex A75

This patch also fixes the assumption that the counters are disabled on
the resume path. This is incorrect as the AMU counters are enabled
early in the CPU reset function before `cpuamu_context_restore()`
runs.

Change-Id: I38a94eb166a523f00de18e86860434ffccff2131
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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Factor out CPU AMU helpers

This patch also fixes `cpuamu_write_cpuamcntenclr_el0()` to use an MSR
instruction instead of an MRS instruction.

Change-Id: Ia6531f64b5ebc60ba432124eaa8d8eaccba40ed0
Sig

Factor out CPU AMU helpers

This patch also fixes `cpuamu_write_cpuamcntenclr_el0()` to use an MSR
instruction instead of an MRS instruction.

Change-Id: Ia6531f64b5ebc60ba432124eaa8d8eaccba40ed0
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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MISRA fixes for AMU/SPE and SVE

Change-Id: I38470528111410cf12b187eb1397d87b812c9416
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

aarch32: Fix multiple bugs in amu_helpers.S

AArch32 uses odd-even pairs when passing 64-bit arguments to
functions. For example in `amu_group0_cnt_write_internal()` the
second argument is a uint64_

aarch32: Fix multiple bugs in amu_helpers.S

AArch32 uses odd-even pairs when passing 64-bit arguments to
functions. For example in `amu_group0_cnt_write_internal()` the
second argument is a uint64_t which is passed in r2 and r3.

In `amu_group1_set_evtype_internal()` the value that needs to be
written to the system register is in r1 not in r0.

Change-Id: I20196268fdb1dc9ef6c4ebe61e761fba9623b3f2
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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Assert that group0/group1 counter config is what we expect

Before suspend the AMU counters should be enabled and after resume
they should be disabled. Assert that to be consistent with the
AArch64

Assert that group0/group1 counter config is what we expect

Before suspend the AMU counters should be enabled and after resume
they should be disabled. Assert that to be consistent with the
AArch64 implementation of `amu_context_{save,restore}()`.

Change-Id: Ia46f77e4062b93afb93721a2890a9b9d2a7f300e
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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Implement {spe,sve}_supported() helpers and refactor code

Implement helpers to test if the core supports SPE/SVE. We have a
similar helper for AMU and this patch makes all extensions consistent
in

Implement {spe,sve}_supported() helpers and refactor code

Implement helpers to test if the core supports SPE/SVE. We have a
similar helper for AMU and this patch makes all extensions consistent
in their implementation.

Change-Id: I3e6f7522535ca358259ad142550b19fcb883ca67
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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Fixup AArch32 errata printing framework

The AArch32 assembly implementation of `print_errata_status` did not save
a register which was getting clobbered by a `get_cpu_ops_ptr`. This
patch fixes that

Fixup AArch32 errata printing framework

The AArch32 assembly implementation of `print_errata_status` did not save
a register which was getting clobbered by a `get_cpu_ops_ptr`. This
patch fixes that.

Change-Id: Id0711e46b7c685a18a10328d4b513e952a5d860b
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1258 from vchong/optee_dbg

optee: print header info before validate

Merge pull request #1260 from sandrine-bailleux-arm/topics/sb/fix-zlib-build

zlib: Fix build error when LOG_LEVEL=50

zlib: Fix build error when LOG_LEVEL=50

When enabling VERBOSE() traces, the zlib library fails to compile
because of an incompatible format specifier string. Fix that.

Change-Id: I74ff1c8dc2e6157ee

zlib: Fix build error when LOG_LEVEL=50

When enabling VERBOSE() traces, the zlib library fails to compile
because of an incompatible format specifier string. Fix that.

Change-Id: I74ff1c8dc2e6157ee982f7754bce4504599e3013
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge pull request #1254 from masahir0y/bl2-at-el3

Fix zero_normalmem() for BL2_AT_EL3

optee: print header info before validate

Currently optee header info is only printed after it is validated,
but this does not help with debugging in case of error, so print it
before.

Signed-off-by

optee: print header info before validate

Currently optee header info is only printed after it is validated,
but this does not help with debugging in case of error, so print it
before.

Signed-off-by: Victor Chong <victor.chong@linaro.org>

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Merge pull request #1173 from etienne-lms/armv7-qemu

support to boot OP-TEE on AArch32/Armv7+example with Cortex-A15/Qemu

Merge pull request #1224 from masahir0y/gzip

Support GZIP-compressed images for faster loading and verification