Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity deadcode issue
fix(zlib): fix overflow issue from coverity

Merge changes from topic "tc-lsc-25-cpu-libs" into integration

* changes:
feat(cpus): add support for LSC25 E-core CPU
feat(cpus): add support for LSC25 P-core CPU

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).

This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b

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Merge "fix(gpt): remove unused `gpt_disable` function" into integration

Merge "fix(psci): get the cpu_ops before exiting coherency" into integration

fix(gpt): remove unused `gpt_disable` function

After GPT protections are enabled, there are no scenarios where they
need to be disabled, similarly to how TZC-400 protections are not
disabled after b

fix(gpt): remove unused `gpt_disable` function

After GPT protections are enabled, there are no scenarios where they
need to be disabled, similarly to how TZC-400 protections are not
disabled after being setup.

Change-Id: I7eae3147130c7a6c3b7b3e9c10e8e7229f32505d
Signed-off-by: Ludovic Mermod <ludovic.mermod@arm.com>

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fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
priva

fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
private caches (usually the L1). However, the destination might be
shared caches (eg DSU L2 cache) so when we subsequently dereference the
cpu_data pointer we could get a stale value.

So dereference it prior to disabling the caches to avoid this scenario
and do all accesses from a coherent view of memory.

Change-Id: If118ca8c0436dd04d6ad0d57073d69305a7f41cb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without en

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without enabling
FEAT_AMUv1p1. As a result, the AMU_RESTRICT_COUNTERS may not take
effect, making this configuration potentially insecure.

Fix this by adding a constraints and rejigging auxiliary counter enables
such that they only happen when FEAT_AMUv1p1 has been enabled so that's
more apparent.

Change-Id: I5b5061d603013598f07d70401d68915c016a1a1b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan

feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan

feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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fix(libfdt): fix coverity reported issue

Check for null pointer before usage of prop.

Coverity Reports -
CID 394590: (#1 of 1): Dereference null return value (NULL_RETURNS)
6. dereference: Derefere

fix(libfdt): fix coverity reported issue

Check for null pointer before usage of prop.

Coverity Reports -
CID 394590: (#1 of 1): Dereference null return value (NULL_RETURNS)
6. dereference: Dereferencing a pointer that might be NULL prop when
calling fdt_setprop.

Change-Id: I2f864a1b476ef4a22f34d8157e1176354b996172
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(libc): fix coverity deadcode issue

Comparison checks makes no sense due to the way libc
in TF-A has implemeneted long and long long which are the same
so checking for overflow is deadcode.

Cove

fix(libc): fix coverity deadcode issue

Comparison checks makes no sense due to the way libc
in TF-A has implemeneted long and long long which are the same
so checking for overflow is deadcode.

Coverity reports -
CID 493664: (#1 of 1): Logically dead code (DEADCODE)

The cutoff and cutlim check is good enough to avoid any overflow.
So remove overflow checks added.

Change-Id: I83e4197e5107bf7c5edc8050bc831b721454573b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(zlib): fix overflow issue from coverity

Fix the overflow when m equals 0 in the multmodp function during the
for loop. As identified by coverity report.

Reported as -

CID 427579: (#1 of 1): Ov

fix(zlib): fix overflow issue from coverity

Fix the overflow when m equals 0 in the multmodp function during the
for loop. As identified by coverity report.

Reported as -

CID 427579: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)
163. overflow_const: Expression m - 1UL, where m is known to be equal
to 0, underflows the type of m - 1UL, which is type unsigned long.

Change-Id: Idb0238bc8c7ff11f1fc22f4b69deef3d3ed4acb6
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with o

Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with out-of-bounds read
fix(fvp): fix coverity issue unsigned_compare

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feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.

The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.

The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.

FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.

This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.

This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5

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feat(per-cpu): migrate amu_ctx to per-cpu framework

migrate amu_ctx object to the NUMA-aware per-cpu framework
to optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Jos

feat(per-cpu): migrate amu_ctx to per-cpu framework

migrate amu_ctx object to the NUMA-aware per-cpu framework
to optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I55e5e923ddd7307039e0cd9a35e91d908f910d10

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feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-of

feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Change-Id: Ie8b9f4eea8c61d4de9996d9370634cbd08ff1d8d

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feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signe

feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idec3e3b74ecf03b420b339a183be2b9e00f8a78f

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feat(per-cpu): integrate per-cpu framework into BL31/BL32

Integrate per-cpu support into BL31/BL32 by extending the following
areas:

Zero-initialization: Treats per-cpu sections like .bss and clear

feat(per-cpu): integrate per-cpu framework into BL31/BL32

Integrate per-cpu support into BL31/BL32 by extending the following
areas:

Zero-initialization: Treats per-cpu sections like .bss and clears them
during early C runtime initialization. For platforms that enable
NUMA_AWARE_PER_CPU, invokes a platform hook to zero-initialize
node-specific per-cpu regions.

Cache maintenance: Extends the BL31 exit path to clean dcache lines
covering the per-cpu region, ensuring data written by the primary core
is visible to secondary cores.

tpidr_el3 setup: Initializes tpidr_el3 with the base address of the
current CPU’s per-cpu section. This allows per-cpu framework to
resolve local cpu accesses efficiently.

The percpu_data object is currently stored in tpidr_el3. Since the
per-cpu framework will use tpidr_el3 for this-cpu access, percpu_data
must be migrated to avoid conflict. This commit moves percpu_data to
the per-cpu framework.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iff0c2e1f8c0ebd25c4bb0b09bfe15dd4fbe20561

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feat(per-cpu): introduce framework accessors/definers

Introduce per-cpu framework definers and accessors for allocation and
access of per-cpu objects. The accessors support "per_cpu_cur" variants
fo

feat(per-cpu): introduce framework accessors/definers

Introduce per-cpu framework definers and accessors for allocation and
access of per-cpu objects. The accessors support "per_cpu_cur" variants
for access on the calling CPU as well as "per_cpu_by_index" variants for
access on any CPU. Additionally, the framework supports NUMA-aware
allocation, allowing the per-cpu data to be distributed across different
memory nodes. This enables the system to allocate per-cpu data on memory
nodes closest to the respective CPU, optimising memory access and
performance.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8361602ff626dcfe9405e7e2a28c5d143aaac574

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feat(cpufeat): introduce FEAT_RME_GDI support

This patch adds a new build flag ENABLE_FEAT_RME_GDI to enable this
feature, along with defining various related register fields. At this
point, when en

feat(cpufeat): introduce FEAT_RME_GDI support

This patch adds a new build flag ENABLE_FEAT_RME_GDI to enable this
feature, along with defining various related register fields. At this
point, when enabled, this feature enables the SA and NSP GPI encodings
by setting the corresponding bits in GPCCR_EL3.

Change-Id: I54152fbb3d19b176264e5d16acbcc866725dc290
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Timothy Hayes <timothy.hayes@arm.com>

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feat(cpufeat): add support for FEAT_RME_GPC2

This change adds support for FEAT_RME_GPC2 and Non-Secure-Only (NSO)
Physical Address Space.

Previously, all non-secure (NS) memory was accessible to th

feat(cpufeat): add support for FEAT_RME_GPC2

This change adds support for FEAT_RME_GPC2 and Non-Secure-Only (NSO)
Physical Address Space.

Previously, all non-secure (NS) memory was accessible to the secure
world and realm world. With GPC2 and the NSO bit in the GPT, memory
can now be restricted to the non-secure world only. This is enabled
automatically on supported systems when ENABLE_RME is true.

Change-Id: I9b70c3a23c5ec7d83bd787d0fb3edd55934f1d05
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Girish Pathak <girish.pathak@arm.com>

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fix(libc): fix coverity overflowed constant

Avoid overflow that may occur from math operations.

Coverity message:
-----------------
CID 457888: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)34.

fix(libc): fix coverity overflowed constant

Avoid overflow that may occur from math operations.

Coverity message:
-----------------
CID 457888: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)34.
overflow_const: Expression acc, where base is known to be equal to 16,
overflows the type of acc, which is type unsigned long long.

Change-Id: I41f22e22625a17826b2cedff101120918e23c8e8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(libc): fix coverity overflowed constant

Assigning acc which of type unsigned long(long) with (L)LONG_MAX or (L)LONG_MIN
will cause a overflow of type acc.

Coverity Message:
-----------------
Ov

fix(libc): fix coverity overflowed constant

Assigning acc which of type unsigned long(long) with (L)LONG_MAX or (L)LONG_MIN
will cause a overflow of type acc.

Coverity Message:
-----------------
Overflowed constant (INTEGER_OVERFLOW)
overflow_const: Expression acc, where
neg ? -9223372036854775808L : 9223372036854775807L is known to be equal
to -9223372036854775808, underflows the type of acc, which is type
unsigned long.

Change-Id: Ic97c3ad8a2a281dfe7ef6b28b2500fd48e45f19e
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(psci): fix coverity issue with out-of-bounds read

Avoid OVERRUN on parent indices if accidental return negative value
from `get_pwr_lvl_state_idx`, so convert everything to use unsigned
int to a

fix(psci): fix coverity issue with out-of-bounds read

Avoid OVERRUN on parent indices if accidental return negative value
from `get_pwr_lvl_state_idx`, so convert everything to use unsigned
int to avoid Out-of-bounds read (OVERRUN)

Change-Id: Ie6d6fd34db9903e99b29e004fb46908aea8acd46
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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