1 /* 2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <common/debug.h> 12 #include <plat/common/platform.h> 13 14 #include "psci_private.h" 15 16 #ifndef PLAT_MAX_PWR_LVL_STATES 17 #define PLAT_MAX_PWR_LVL_STATES 2U 18 #endif 19 20 /* Following structure is used for PSCI STAT */ 21 typedef struct psci_stat { 22 u_register_t residency; 23 u_register_t count; 24 } psci_stat_t; 25 26 /* 27 * Following is used to keep track of the last cpu 28 * that goes to power down in non cpu power domains. 29 */ 30 static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = { 31 [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS - 1U] = -1}; 32 33 /* 34 * Following are used to store PSCI STAT values for 35 * CPU and non CPU power domains. 36 */ 37 static psci_stat_t psci_cpu_stat[PLATFORM_CORE_COUNT] 38 [PLAT_MAX_PWR_LVL_STATES]; 39 static psci_stat_t psci_non_cpu_stat[PSCI_NUM_NON_CPU_PWR_DOMAINS] 40 [PLAT_MAX_PWR_LVL_STATES]; 41 42 /* 43 * This functions returns the index into the `psci_stat_t` array given the 44 * local power state and power domain level. If the platform implements the 45 * `get_pwr_lvl_state_idx` pm hook, then that will be used to return the index. 46 */ 47 static unsigned int get_stat_idx(plat_local_state_t local_state, unsigned int pwr_lvl) 48 { 49 unsigned int idx; 50 51 if (psci_plat_pm_ops->get_pwr_lvl_state_idx == NULL) { 52 assert(PLAT_MAX_PWR_LVL_STATES == 2U); 53 if (is_local_state_retn(local_state) != 0) 54 return 0; 55 56 assert(is_local_state_off(local_state) != 0); 57 return 1; 58 } 59 60 idx = psci_plat_pm_ops->get_pwr_lvl_state_idx(local_state, pwr_lvl); 61 assert(idx < PLAT_MAX_PWR_LVL_STATES); 62 return idx; 63 } 64 65 /******************************************************************************* 66 * This function is passed the target local power states for each power 67 * domain (state_info) between the current CPU domain and its ancestors until 68 * the target power level (end_pwrlvl). 69 * 70 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it 71 * updates the `last_cpu_in_non_cpu_pd[]` with last power down cpu id. 72 * 73 * This function will only be invoked with data cache enabled and while 74 * powering down a core. 75 ******************************************************************************/ 76 void psci_stats_update_pwr_down(unsigned int cpu_idx, unsigned int end_pwrlvl, 77 const psci_power_state_t *state_info) 78 { 79 unsigned int lvl, parent_idx; 80 81 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 82 assert(state_info != NULL); 83 84 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 85 86 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 87 88 /* Break early if the target power state is RUN */ 89 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) 90 break; 91 92 /* 93 * The power domain is entering a low power state, so this is 94 * the last CPU for this power domain 95 */ 96 last_cpu_in_non_cpu_pd[parent_idx] = (int)cpu_idx; 97 98 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 99 } 100 101 } 102 103 /******************************************************************************* 104 * This function updates the PSCI STATS(residency time and count) for CPU 105 * and NON-CPU power domains. 106 * It is called with caches enabled and locks acquired(for NON-CPU domain) 107 ******************************************************************************/ 108 void psci_stats_update_pwr_up(unsigned int cpu_idx, unsigned int end_pwrlvl, 109 const psci_power_state_t *state_info) 110 { 111 unsigned int lvl, parent_idx; 112 unsigned int stat_idx; 113 plat_local_state_t local_state; 114 u_register_t residency; 115 116 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 117 assert(state_info != NULL); 118 119 /* Get the index into the stats array */ 120 local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; 121 stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL); 122 123 /* Call into platform interface to calculate residency. */ 124 residency = plat_psci_stat_get_residency(PSCI_CPU_PWR_LVL, 125 state_info, cpu_idx); 126 127 /* Update CPU stats. */ 128 psci_cpu_stat[cpu_idx][stat_idx].residency += residency; 129 psci_cpu_stat[cpu_idx][stat_idx].count++; 130 131 /* 132 * Check what power domains above CPU were off 133 * prior to this CPU powering on. 134 */ 135 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 136 /* Return early if this is the first power up. */ 137 if (last_cpu_in_non_cpu_pd[parent_idx] == -1) 138 return; 139 140 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 141 local_state = state_info->pwr_domain_state[lvl]; 142 if (is_local_state_run(local_state) != 0) { 143 /* Break early */ 144 break; 145 } 146 147 assert(last_cpu_in_non_cpu_pd[parent_idx] != -1); 148 149 /* Call into platform interface to calculate residency. */ 150 residency = plat_psci_stat_get_residency(lvl, state_info, 151 (unsigned int)last_cpu_in_non_cpu_pd[parent_idx]); 152 153 /* Initialize back to reset value */ 154 last_cpu_in_non_cpu_pd[parent_idx] = -1; 155 156 /* Get the index into the stats array */ 157 stat_idx = get_stat_idx(local_state, lvl); 158 159 /* Update non cpu stats */ 160 psci_non_cpu_stat[parent_idx][stat_idx].residency += residency; 161 psci_non_cpu_stat[parent_idx][stat_idx].count++; 162 163 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 164 } 165 166 } 167 168 /******************************************************************************* 169 * This function returns the appropriate count and residency time of the 170 * local state for the highest power level expressed in the `power_state` 171 * for the node represented by `target_cpu`. 172 ******************************************************************************/ 173 static int psci_get_stat(u_register_t target_cpu, unsigned int power_state, 174 psci_stat_t *psci_stat) 175 { 176 int rc; 177 unsigned int pwrlvl, lvl, parent_idx, target_idx, stat_idx; 178 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 179 plat_local_state_t local_state; 180 181 /* Determine the cpu index */ 182 target_idx = (unsigned int) plat_core_pos_by_mpidr(target_cpu); 183 184 /* Validate the power_state parameter */ 185 if (psci_plat_pm_ops->translate_power_state_by_mpidr == NULL) 186 rc = psci_validate_power_state(power_state, &state_info); 187 else 188 rc = psci_plat_pm_ops->translate_power_state_by_mpidr( 189 target_cpu, power_state, &state_info); 190 191 if (rc != PSCI_E_SUCCESS) 192 return PSCI_E_INVALID_PARAMS; 193 194 /* Find the highest power level */ 195 pwrlvl = psci_find_target_suspend_lvl(&state_info); 196 if (pwrlvl == PSCI_INVALID_PWR_LVL) { 197 ERROR("Invalid target power level for PSCI statistics operation\n"); 198 panic(); 199 } 200 201 /* Get the index into the stats array */ 202 local_state = state_info.pwr_domain_state[pwrlvl]; 203 stat_idx = get_stat_idx(local_state, pwrlvl); 204 205 if (pwrlvl > PSCI_CPU_PWR_LVL) { 206 /* Get the power domain index */ 207 parent_idx = SPECULATION_SAFE_VALUE(psci_cpu_pd_nodes[target_idx].parent_node); 208 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl < pwrlvl; lvl++) 209 parent_idx = SPECULATION_SAFE_VALUE(psci_non_cpu_pd_nodes[parent_idx].parent_node); 210 211 /* Get the non cpu power domain stats */ 212 *psci_stat = psci_non_cpu_stat[parent_idx][stat_idx]; 213 } else { 214 /* Get the cpu power domain stats */ 215 *psci_stat = psci_cpu_stat[target_idx][stat_idx]; 216 } 217 218 return PSCI_E_SUCCESS; 219 } 220 221 /* This is the top level function for PSCI_STAT_RESIDENCY SMC. */ 222 u_register_t psci_stat_residency(u_register_t target_cpu, 223 unsigned int power_state) 224 { 225 psci_stat_t psci_stat; 226 227 /* Validate the target cpu */ 228 if (!is_valid_mpidr(target_cpu)) 229 return 0; 230 231 int rc = psci_get_stat(target_cpu, power_state, &psci_stat); 232 233 if (rc == PSCI_E_SUCCESS) 234 return psci_stat.residency; 235 else 236 return 0; 237 } 238 239 /* This is the top level function for PSCI_STAT_COUNT SMC. */ 240 u_register_t psci_stat_count(u_register_t target_cpu, 241 unsigned int power_state) 242 { 243 psci_stat_t psci_stat; 244 245 /* Validate the target cpu */ 246 if (!is_valid_mpidr(target_cpu)) 247 return 0; 248 249 int rc = psci_get_stat(target_cpu, power_state, &psci_stat); 250 251 if (rc == PSCI_E_SUCCESS) 252 return psci_stat.count; 253 else 254 return 0; 255 } 256