1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2024, The Linux Foundation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <common_def.h> 12 13 #include <qti_board_def.h> 14 #include <qtiseclib_defs_plat.h> 15 16 /*----------------------------------------------------------------------------*/ 17 18 /*----------------------------------------------------------------------------*/ 19 /* 20 * MPIDR_PRIMARY_CPU 21 * You just need to have the correct core_affinity_val i.e. [7:0] 22 * and cluster_affinity_val i.e. [15:8] 23 * the other bits will be ignored 24 */ 25 /*----------------------------------------------------------------------------*/ 26 #define MPIDR_PRIMARY_CPU 0x0000 27 /*----------------------------------------------------------------------------*/ 28 29 #define QTI_PWR_LVL0 MPIDR_AFFLVL0 30 #define QTI_PWR_LVL1 MPIDR_AFFLVL1 31 #define QTI_PWR_LVL2 MPIDR_AFFLVL2 32 #define QTI_PWR_LVL3 MPIDR_AFFLVL3 33 34 /* 35 * Macros for local power states encoded by State-ID field 36 * within the power-state parameter. 37 */ 38 /* Local power state for power domains in Run state. */ 39 #define QTI_LOCAL_STATE_RUN 0 40 /* 41 * Local power state for clock-gating. Valid only for CPU and not cluster power 42 * domains 43 */ 44 #define QTI_LOCAL_STATE_STB 1 45 /* 46 * Local power state for retention. Valid for CPU and cluster power 47 * domains 48 */ 49 #define QTI_LOCAL_STATE_RET 2 50 /* 51 * Local power state for OFF/power down. Valid for CPU, cluster, RSC and PDC 52 * power domains 53 */ 54 #define QTI_LOCAL_STATE_OFF 3 55 /* 56 * Local power state for DEEPOFF/power rail down. Valid for CPU, cluster and RSC 57 * power domains 58 */ 59 #define QTI_LOCAL_STATE_DEEPOFF 4 60 61 /* 62 * This macro defines the deepest retention state possible. A higher state 63 * id will represent an invalid or a power down state. 64 */ 65 #define PLAT_MAX_RET_STATE QTI_LOCAL_STATE_RET 66 67 /* 68 * This macro defines the deepest power down states possible. Any state ID 69 * higher than this is invalid. 70 */ 71 #define PLAT_MAX_OFF_STATE QTI_LOCAL_STATE_DEEPOFF 72 73 /****************************************************************************** 74 * Required platform porting definitions common to all ARM standard platforms 75 *****************************************************************************/ 76 77 /* 78 * Platform specific page table and MMU setup constants. 79 */ 80 #define MAX_MMAP_REGIONS (PLAT_QTI_MMAP_ENTRIES) 81 82 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36) 83 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36) 84 85 #define ARM_CACHE_WRITEBACK_SHIFT 6 86 87 /* 88 * Some data must be aligned on the biggest cache line size in the platform. 89 * This is known only to the platform as it might have a combination of 90 * integrated and external caches. 91 */ 92 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 93 94 /* 95 * One cache line needed for bakery locks on ARM platforms 96 */ 97 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 98 99 /*----------------------------------------------------------------------------*/ 100 /* PSCI power domain topology definitions */ 101 /*----------------------------------------------------------------------------*/ 102 /* One domain each to represent RSC and PDC level */ 103 #define PLAT_PDC_COUNT 1 104 #define PLAT_RSC_COUNT 1 105 106 /* There is one top-level FCM cluster */ 107 #define PLAT_CLUSTER_COUNT 1 108 109 /* No. of cores in the FCM cluster */ 110 #define PLAT_CLUSTER0_CORE_COUNT 8 111 112 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER0_CORE_COUNT) 113 114 #define PLAT_NUM_PWR_DOMAINS (PLAT_PDC_COUNT +\ 115 PLAT_RSC_COUNT +\ 116 PLAT_CLUSTER_COUNT +\ 117 PLATFORM_CORE_COUNT) 118 119 #define PLAT_MAX_PWR_LVL 3 120 121 /*****************************************************************************/ 122 /* Memory mapped Generic timer interfaces */ 123 /*****************************************************************************/ 124 125 /*----------------------------------------------------------------------------*/ 126 /* GIC-600 constants */ 127 /*----------------------------------------------------------------------------*/ 128 #define BASE_GICD_BASE 0x17A00000 129 #define BASE_GICR_BASE 0x17A60000 130 #define BASE_GICC_BASE 0x0 131 #define BASE_GICH_BASE 0x0 132 #define BASE_GICV_BASE 0x0 133 134 #define QTI_GICD_BASE BASE_GICD_BASE 135 #define QTI_GICR_BASE BASE_GICR_BASE 136 #define QTI_GICC_BASE BASE_GICC_BASE 137 138 /*----------------------------------------------------------------------------*/ 139 140 /*----------------------------------------------------------------------------*/ 141 /* UART related constants. */ 142 /*----------------------------------------------------------------------------*/ 143 #define PLAT_QTI_UART_BASE 0x880000 144 /* BASE ADDRESS OF DIFFERENT REGISTER SPACES IN HW */ 145 #define GENI4_CFG 0x0 146 #define GENI4_IMAGE_REGS 0x100 147 #define GENI4_DATA 0x600 148 149 /* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */ 150 #define GENI_STATUS_REG (GENI4_CFG + 0x00000040) 151 #define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK (0x1) 152 #define UART_TX_TRANS_LEN_REG (GENI4_IMAGE_REGS + 0x00000170) 153 /* MASTER/TX ENGINE REGISTERS */ 154 #define GENI_M_CMD0_REG (GENI4_DATA + 0x00000000) 155 /* FIFO, STATUS REGISTERS AND MASKS */ 156 #define GENI_TX_FIFOn_REG (GENI4_DATA + 0x00000100) 157 158 #define GENI_M_CMD_TX (0x08000000) 159 160 /*----------------------------------------------------------------------------*/ 161 /* Peripherals base addresses */ 162 /*----------------------------------------------------------------------------*/ 163 #define QTI_SEC_PRNG_BASE 0x790000 164 165 /*----------------------------------------------------------------------------*/ 166 /* Device address space for mapping. Excluding starting 4K */ 167 /*----------------------------------------------------------------------------*/ 168 #define QTI_DEVICE_BASE 0x1000 169 #define QTI_DEVICE_SIZE (0x80000000 - QTI_DEVICE_BASE) 170 171 /******************************************************************************* 172 * BL31 specific defines. 173 ******************************************************************************/ 174 /* 175 * Put BL31 at DDR as per memory map. BL31_BASE is calculated using the 176 * current BL31 debug size plus a little space for growth. 177 */ 178 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 179 180 /*----------------------------------------------------------------------------*/ 181 /* AOSS registers */ 182 /*----------------------------------------------------------------------------*/ 183 #define QTI_PS_HOLD_REG 0x0C264000 184 /*----------------------------------------------------------------------------*/ 185 /* AOP CMD DB address space for mapping */ 186 /*----------------------------------------------------------------------------*/ 187 #define QTI_AOP_CMD_DB_BASE 0x85F20000 188 #define QTI_AOP_CMD_DB_SIZE 0x00020000 189 /*----------------------------------------------------------------------------*/ 190 /* SOC hw version register */ 191 /*----------------------------------------------------------------------------*/ 192 #define QTI_SOC_VERSION_MASK U(0xFFFF) 193 #define QTI_SOC_REVISION_REG 0x1FC8000 194 #define QTI_SOC_REVISION_MASK U(0xFFFF) 195 /*----------------------------------------------------------------------------*/ 196 /* LC PON register offsets */ 197 /*----------------------------------------------------------------------------*/ 198 #define PON_PS_HOLD_RESET_CTL 0x85a 199 #define PON_PS_HOLD_RESET_CTL2 0x85b 200 /*----------------------------------------------------------------------------*/ 201 202 #endif /* PLATFORM_DEF_H */ 203