refactor(psci): make CMOs target the whole psci_cpu_data_t

psci_cpu_data_t is tiny - on AArch64 it's 12 bytes. Cache maintenance
operations (CMOs) operate on cache lines which are much bigger - usua

refactor(psci): make CMOs target the whole psci_cpu_data_t

psci_cpu_data_t is tiny - on AArch64 it's 12 bytes. Cache maintenance
operations (CMOs) operate on cache lines which are much bigger - usually
64 bytes long. As such, issuing a cache clean for a member in the middle
of psci_cpu_data_t won't necessarily have the expected effect. The
member will be cleaned, sure, but so will the rest of the cache line
along with it. If the struct happens to straddle cache lines this will
lead to the next 52 bytes, most of which not belonging to
psci_cpu_data_t, being cleaned as well and the start of psci_cpu_data_t
not being cleaned at all.

This is not a problem because of the per-cpu (and cpu_data before it)
section - it is cache size aligned and all data within a single section
belongs to the same core so overdoing cache cleans won't have strange
side effects.

Regardless, this patch clarifies CMOs around psci_cpu_data_t by always
targeting the whole structure. To make sure there is never a situation
where it straddles cache lines and this causes weird side effect, its
alignment is set to the size of the structure to make sure it is always
on the same cache line.

Change-Id: I5d82ee6bb2ce0ed3c6a7e4abb7aa890f5e3bd0af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(psci): set requested local power states in failure path" into integration

Merge "fix(psci): gate suspend end_pwrlvl override in OS_INIT mode at runtime" into integration

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've gained
lots of quality of life features that allow for better feature
enablement. This patch converts USE_SPINLOCK_CAS to tri-state and adds
it to FEATURE_DETECTION to align with all other features.

Instead of introducing the assembly checking for tri-state, this patch
translates all locking routines to C inline assembly and uses the
standard C helpers. The main benefit is that this gives greater
visibility to the compiler about what the functions are doing and lets
it optimise better. Namely, it is able to allocate registers itself and
inline the functions when LTO is enabled.

An unsuccessful attempt was made to use the instructions directly and
have even flow control in C. This, however, made code very complicated
and less efficient in the tight loops of the spinlock.

The last use of ARM_ARCH_AT_LEAST goes away with this change and so this
macro is removed. It has now been fully superseded by the FEAT_STATE
framework.

This change exposes a limitation - RME_GPT_BITLOCK_BLOCK requires
USE_SPINLOCK_CAS. This patch does not address this in any way but makes
the relationship explicit.

Change-Id: I580081549aceded2dca3e0f4564ee7510a7e56ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(psci): gate suspend end_pwrlvl override in OS_INIT mode at runtime

This change adds an additional runtime gate to override the
suspend power level. The build-time check already existed, but
it's

fix(psci): gate suspend end_pwrlvl override in OS_INIT mode at runtime

This change adds an additional runtime gate to override the
suspend power level. The build-time check already existed, but
it's possible that PSCI might not be in OS_INIT mode. In that
case, no override should occur.

Change-Id: I695cef3f4ddd8957360fe056c8715c170df6f1f4
Signed-off-by: Bill Peckham <bpeckham@google.com>
Signed-off-by: Karunatharaka Bodduluri <karunatharaka@google.com>

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fix(psci): set requested local power states in failure path

In OS initiated coordination, it's possible that the platform
function pwr_domain_validate_suspend may return a non-success
value. In that

fix(psci): set requested local power states in failure path

In OS initiated coordination, it's possible that the platform
function pwr_domain_validate_suspend may return a non-success
value. In that case, PSCI must set the
psci_req_local_pwr_states values to run.

Change-Id: I2c94af024935ab156c806b90a7094c40e1667fb7
Signed-off-by: Bill Peckham <bpeckham@google.com>
Signed-off-by: Karunatharaka Bodduluri <karunatharaka@google.com>

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fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
priva

fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
private caches (usually the L1). However, the destination might be
shared caches (eg DSU L2 cache) so when we subsequently dereference the
cpu_data pointer we could get a stale value.

So dereference it prior to disabling the caches to avoid this scenario
and do all accesses from a coherent view of memory.

Change-Id: If118ca8c0436dd04d6ad0d57073d69305a7f41cb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with o

Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with out-of-bounds read
fix(fvp): fix coverity issue unsigned_compare

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feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.

The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.

The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.

FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.

This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.

This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5

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feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-of

feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Change-Id: Ie8b9f4eea8c61d4de9996d9370634cbd08ff1d8d

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feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signe

feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idec3e3b74ecf03b420b339a183be2b9e00f8a78f

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fix(psci): fix coverity issue with out-of-bounds read

Avoid OVERRUN on parent indices if accidental return negative value
from `get_pwr_lvl_state_idx`, so convert everything to use unsigned
int to a

fix(psci): fix coverity issue with out-of-bounds read

Avoid OVERRUN on parent indices if accidental return negative value
from `get_pwr_lvl_state_idx`, so convert everything to use unsigned
int to avoid Out-of-bounds read (OVERRUN)

Change-Id: Ie6d6fd34db9903e99b29e004fb46908aea8acd46
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint

We've charged the PSCI entrypoint with doing BL31 specific things like
setting up the EL3 context and doing feature detection.

refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint

We've charged the PSCI entrypoint with doing BL31 specific things like
setting up the EL3 context and doing feature detection. Well, this is
irrelevant for sp_min and not really appropriate for PSCI. So move it to
the bl31_warmboot() function to reflect this correctly and bring the
feature detection a bit earlier, hopefully spotting more errors.

This allows for a pair of minor cleanups - we can pass the core_pos to
psci_warmboot_entrypoint() without having to refetch it, and we can put
the pauth enablement in cm_manage_extensions_el3() along with all
others. The call of that function is kept after the MMU is turned on so
that we have nicer (coherent) access to cpu_data.

Change-Id: Id031cfa0e1d8fe98919a14f9db73eb5bc9e00f67
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(smccc): resolve caller world confusion" into integration

Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_op

Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C
fix(aarch32): make get_cpu_ops_ptr() PCS compliant

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refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of

refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of assembly was
that the get_cpu_ops_ptr() function was not PCS compliant and needed a
wrapper to do that instead. That has now been fixed so move this to C so
it's more readable and more optimise-able by the compiler.

Change-Id: I5fcfe8ddb122dd35d58adc6d44a7484c5c595815
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(psci): add missing curly braces" into integration

Merge "fix(psci): initialise variable to default zero" into integration

fix(smccc): resolve caller world confusion

TF-A checks the SMC caller world using is_caller_secure,
is_caller_non_secure and is_caller_realm macros. Until
realm world was introduced it was fine to u

fix(smccc): resolve caller world confusion

TF-A checks the SMC caller world using is_caller_secure,
is_caller_non_secure and is_caller_realm macros. Until
realm world was introduced it was fine to use a pattern like

if (is_caller_non_secure(flags))
return DENY;

// Handle secure call
secure_operation();

is_caller_non_secure would be false for a realm caller, so this pattern
treats this like a secure world caller. This patch fixes
improper use of is_caller_non_secure and is_caller_secure
to handle realm world caller properly.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I60b125853183ac2ac15277f06d2efb7f3a9d3977

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fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body w

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: Ida2460b7fe6f27b23382a1259a5ac93fe36bd48d
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(psci): initialize the variables

This corrects the MISRA violation C2012-9.1:
All variables are explicitly initialized with zero or default values
during declaration. This helps, even if a functi

fix(psci): initialize the variables

This corrects the MISRA violation C2012-9.1:
All variables are explicitly initialized with zero or default values
during declaration. This helps, even if a function fails, the
variables contain predictable values, preventing undefined behavior

Change-Id: I910467fd03e434e32da01e421fe77ec1402bc15a
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:
The value of an object with automatic storage duration shall not
be read before it has been set.
Initializ

fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:
The value of an object with automatic storage duration shall not
be read before it has been set.
Initialized the variable to default value zero.

Change-Id: I225ae4487b05fc47728222765029d6e1fe292ac1
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(lib): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I

fix(lib): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I979ba118fd209be5d4f0bff3978479c22428d79b
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(cpufeat): do feature detection on secondary cores too

Feature detection currently only happens on the boot core, however, it
is possible to have asymmetry between cores. TF-A supports limited s

feat(cpufeat): do feature detection on secondary cores too

Feature detection currently only happens on the boot core, however, it
is possible to have asymmetry between cores. TF-A supports limited such
configurations so it should check secondary cores too.

Change-Id: Iee4955714685be9ae6a017af4a6c284e835ff299
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(psci): optimise clock init on a pabandon

When a powerdown abandon happens, all state will be preserved. As such,
there is no need to re-initialise the timer counter when unwinding.

Change-Id:

feat(psci): optimise clock init on a pabandon

When a powerdown abandon happens, all state will be preserved. As such,
there is no need to re-initialise the timer counter when unwinding.

Change-Id: I64185792a118fd04ca036abbb9be8f670d0d8328
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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