1// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 2/* 3 * ARM Ltd. Fast Models 4 * 5 * Architecture Envelope Model (AEM) ARMv8-A 6 * ARMAEMv8AMPCT 7 * 8 * RTSM_VE_AEMv8A.lisa 9 * 10 * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <services/sdei_flags.h> 15 16#define LEVEL 0 17#define EDGE 2 18#define SDEI_NORMAL 0x70 19#define HIGHEST_SEC 0 20 21#include "rtsm_ve-motherboard.dtsi" 22 23/ { 24 model = "FVP Base"; 25 compatible = "arm,fvp-base", "arm,vexpress"; 26 interrupt-parent = <&gic>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { 31 stdout-path = "serial0:115200n8"; 32 bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on"; 33 }; 34 35 aliases { 36 serial0 = &v2m_serial0; 37 serial1 = &v2m_serial1; 38 serial2 = &v2m_serial2; 39 serial3 = &v2m_serial3; 40 }; 41 42 psci { 43 compatible = "arm,psci-1.0", "arm,psci-0.2"; 44 method = "smc"; 45 max-pwr-lvl = <2>; 46 }; 47 48#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF 49 firmware { 50#if SDEI_IN_FCONF 51 sdei { 52 compatible = "arm,sdei-1.0"; 53 method = "smc"; 54 private_event_count = <3>; 55 shared_event_count = <3>; 56 /* 57 * Each event descriptor has typically 3 fields: 58 * 1. Event number 59 * 2. Interrupt number the event is bound to or 60 * if event is dynamic, specified as SDEI_DYN_IRQ 61 * 3. Bit map of event flags 62 */ 63 private_events = <1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 64 <1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 65 <1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 66 shared_events = <2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 67 <2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 68 <2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 69 }; 70#endif /* SDEI_IN_FCONF */ 71 72#if SEC_INT_DESC_IN_FCONF 73 sec_interrupts { 74 compatible = "arm,secure_interrupt_desc"; 75 /* Number of G0 and G1 secure interrupts defined by the platform */ 76 g0_intr_cnt = <2>; 77 g1s_intr_cnt = <9>; 78 /* 79 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 80 * terminology. Each interrupt property descriptor has 3 fields: 81 * 1. Interrupt number 82 * 2. Interrupt priority 83 * 3. Type of interrupt (Edge or Level configured) 84 */ 85 g0_intr_desc = < 8 SDEI_NORMAL EDGE>, 86 <14 HIGHEST_SEC EDGE>; 87 88 g1s_intr_desc = < 9 HIGHEST_SEC EDGE>, 89 <10 HIGHEST_SEC EDGE>, 90 <11 HIGHEST_SEC EDGE>, 91 <12 HIGHEST_SEC EDGE>, 92 <13 HIGHEST_SEC EDGE>, 93 <15 HIGHEST_SEC EDGE>, 94 <29 HIGHEST_SEC LEVEL>, 95 <56 HIGHEST_SEC LEVEL>, 96 <57 HIGHEST_SEC LEVEL>; 97 }; 98#endif /* SEC_INT_DESC_IN_FCONF */ 99 }; 100#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */ 101 102 cpus { 103 #address-cells = <2>; 104 #size-cells = <0>; 105 106 CPU_MAP 107 108 idle-states { 109 entry-method = "psci"; 110 111 CPU_SLEEP_0: cpu-sleep-0 { 112 compatible = "arm,idle-state"; 113 local-timer-stop; 114 arm,psci-suspend-param = <0x0010000>; 115 entry-latency-us = <40>; 116 exit-latency-us = <100>; 117 min-residency-us = <150>; 118 }; 119 120 CLUSTER_SLEEP_0: cluster-sleep-0 { 121 compatible = "arm,idle-state"; 122 local-timer-stop; 123 arm,psci-suspend-param = <0x1010000>; 124 entry-latency-us = <500>; 125 exit-latency-us = <1000>; 126 min-residency-us = <2500>; 127 }; 128 }; 129 130 CPUS 131 132 L2_0: l2-cache0 { 133 compatible = "cache"; 134 }; 135 }; 136 137 memory@80000000 { 138 device_type = "memory"; 139#if (ENABLE_RME == 1) 140 reg = <0x00000000 0x80000000 0 0x7C000000>, 141 <0x00000008 0x80000000 0 0x80000000>; 142#else 143 reg = <0x00000000 0x80000000 0 0x7F000000>, 144 <0x00000008 0x80000000 0 0x80000000>; 145#endif 146 }; 147 148 reserved-memory { 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 153 /* Chipselect 2,00000000 is physically at 0x18000000 */ 154 vram: vram@18000000 { 155 /* 8 MB of designated video RAM */ 156 compatible = "shared-dma-pool"; 157 reg = <0x00000000 0x18000000 0 0x00800000>; 158 no-map; 159 }; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 165 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 166 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 168 clock-frequency = <100000000>; 169 }; 170 171 timer@2a810000 { 172 compatible = "arm,armv7-timer-mem"; 173 reg = <0x0 0x2a810000 0x0 0x10000>; 174 clock-frequency = <100000000>; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 ranges = <0x0 0x0 0x2a810000 0x100000>; 178 179 frame@2a830000 { 180 frame-number = <1>; 181 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 182 reg = <0x20000 0x10000>; 183 }; 184 }; 185 186 pmu { 187 compatible = "arm,armv8-pmuv3"; 188 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 panel { 192 compatible = "arm,rtsm-display"; 193 port { 194 panel_in: endpoint { 195 remote-endpoint = <&clcd_pads>; 196 }; 197 }; 198 }; 199 200 bus@8000000 { 201 #interrupt-cells = <1>; 202 interrupt-map-mask = <0 0 63>; 203 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 204 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 205 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 206 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 207 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 208 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 209 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 210 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 211 <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 212 <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 213 <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 214 <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 215 <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 216 <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 217 <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 218 <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 219 <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 220 <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 221 <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 222 <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 223 <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 224 <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 225 <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 226 <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 227 <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 228 <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 229 <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 230 <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 231 <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 232 <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 233 <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 234 <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 235 <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 236 <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 237 <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 238 <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 239 <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 240 <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 241 <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 242 <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 243 <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 244 <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 245 <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 246 <0 0 43 &gic 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 247 <0 0 44 &gic 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 248 <0 0 46 &gic 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 249 }; 250 251#if (ENABLE_RME == 1) 252 pci: pci@40000000 { 253 #address-cells = <3>; 254 #size-cells = <2>; 255 #interrupt-cells = <1>; 256 compatible = "pci-host-ecam-generic"; 257 device_type = "pci"; 258 reg = <0x0 0x40000000 0x0 0x10000000>; 259 ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, 260 /* First 3GB of 256GB PCIe memory region 2 */ 261 <0x2000000 0x40 0x00000000 0x40 0x00000000 0x0 0xc0000000>; 262 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 263 <0 0 0 2 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 264 <0 0 0 3 &gic 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 265 <0 0 0 4 &gic 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 266 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 267 msi-map = <0x0 &its 0x0 0x10000>; 268 iommu-map = <0x0 &smmu 0x0 0x10000>; 269 dma-coherent; 270 }; 271 272 smmu: iommu@2b400000 { 273 compatible = "arm,smmu-v3"; 274 reg = <0x0 0x2b400000 0x0 0x100000>; 275 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 276 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 277 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 278 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; 279 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 280 dma-coherent; 281 #iommu-cells = <1>; 282 msi-parent = <&its 0x10000>; 283 }; 284#endif /* ENABLE_RME */ 285}; 286