1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <context.h> 14 #include <lib/cpus/errata.h> 15 #include <lib/el3_runtime/context_mgmt.h> 16 #include <plat/common/platform.h> 17 18 #include "psci_private.h" 19 20 /* 21 * Check that PLATFORM_CORE_COUNT fits into the number of cores 22 * that can be represented by PSCI_MAX_CPUS_INDEX. 23 */ 24 CASSERT(PLATFORM_CORE_COUNT <= (PSCI_MAX_CPUS_INDEX + 1U), assert_psci_cores_overflow); 25 26 /******************************************************************************* 27 * Per cpu non-secure contexts used to program the architectural state prior 28 * return to the normal world. 29 * TODO: Use the memory allocator to set aside memory for the contexts instead 30 * of relying on platform defined constants. 31 ******************************************************************************/ 32 static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT]; 33 static entry_point_info_t warmboot_ep_info[PLATFORM_CORE_COUNT]; 34 35 /****************************************************************************** 36 * Define the psci capability variable. 37 *****************************************************************************/ 38 unsigned int psci_caps; 39 40 /******************************************************************************* 41 * Function which initializes the 'psci_non_cpu_pd_nodes' or the 42 * 'psci_cpu_pd_nodes' corresponding to the power level. 43 ******************************************************************************/ 44 static void __init psci_init_pwr_domain_node(uint16_t node_idx, 45 unsigned int parent_idx, 46 unsigned char level) 47 { 48 if (level > PSCI_CPU_PWR_LVL) { 49 assert(node_idx < PSCI_NUM_NON_CPU_PWR_DOMAINS); 50 51 psci_non_cpu_pd_nodes[node_idx].level = level; 52 psci_lock_init(psci_non_cpu_pd_nodes, node_idx); 53 psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx; 54 psci_non_cpu_pd_nodes[node_idx].local_state = 55 PLAT_MAX_OFF_STATE; 56 } else { 57 psci_cpu_data_t *svc_cpu_data; 58 59 assert(node_idx < PLATFORM_CORE_COUNT); 60 61 psci_cpu_pd_nodes[node_idx].parent_node = parent_idx; 62 63 /* Initialize with an invalid mpidr */ 64 psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR; 65 66 svc_cpu_data = &get_cpu_data_by_index(node_idx, psci_svc_cpu_data); 67 68 /* Set the Affinity Info for the cores as OFF */ 69 svc_cpu_data->aff_info_state = AFF_STATE_OFF; 70 71 /* Default to the highest power level when the cpu is not suspending */ 72 svc_cpu_data->target_pwrlvl = PLAT_MAX_PWR_LVL; 73 74 /* Set the power state to OFF state */ 75 svc_cpu_data->local_state = PLAT_MAX_OFF_STATE; 76 77 psci_flush_dcache_range((uintptr_t)svc_cpu_data, 78 sizeof(*svc_cpu_data)); 79 80 cm_set_context_by_index(node_idx, 81 (void *) &psci_ns_context[node_idx], 82 NON_SECURE); 83 } 84 } 85 86 /******************************************************************************* 87 * This functions updates cpu_start_idx and ncpus field for each of the node in 88 * psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of 89 * the CPUs and check whether they match with the parent of the previous 90 * CPU. The basic assumption for this work is that children of the same parent 91 * are allocated adjacent indices. The platform should ensure this though proper 92 * mapping of the CPUs to indices via plat_core_pos_by_mpidr() and 93 * plat_my_core_pos() APIs. 94 *******************************************************************************/ 95 static void __init psci_update_pwrlvl_limits(void) 96 { 97 unsigned int cpu_idx; 98 int j; 99 unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; 100 unsigned int temp_index[PLAT_MAX_PWR_LVL] = {0}; 101 102 for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { 103 psci_get_parent_pwr_domain_nodes(cpu_idx, 104 PLAT_MAX_PWR_LVL, 105 temp_index); 106 for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { 107 if (temp_index[j] != nodes_idx[j]) { 108 nodes_idx[j] = temp_index[j]; 109 psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx 110 = cpu_idx; 111 } 112 psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++; 113 } 114 } 115 } 116 117 static void __init populate_cpu_data(void) 118 { 119 for (unsigned int idx = 0; idx < psci_plat_core_count; idx++) { 120 set_cpu_data_by_index(idx, warmboot_ep_info, &warmboot_ep_info[idx]); 121 } 122 } 123 124 /******************************************************************************* 125 * Core routine to populate the power domain tree. The tree descriptor passed by 126 * the platform is populated breadth-first and the first entry in the map 127 * informs the number of root power domains. The parent nodes of the root nodes 128 * will point to an invalid entry(-1). 129 ******************************************************************************/ 130 static unsigned int __init populate_power_domain_tree(const unsigned char 131 *topology) 132 { 133 unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl; 134 unsigned int node_index = 0U, num_children; 135 unsigned int parent_node_index = 0U; 136 int level = (int)PLAT_MAX_PWR_LVL; 137 138 /* 139 * For each level the inputs are: 140 * - number of nodes at this level in plat_array i.e. num_nodes_at_level 141 * This is the sum of values of nodes at the parent level. 142 * - Index of first entry at this level in the plat_array i.e. 143 * parent_node_index. 144 * - Index of first free entry in psci_non_cpu_pd_nodes[] or 145 * psci_cpu_pd_nodes[] i.e. node_index depending upon the level. 146 */ 147 while (level >= (int) PSCI_CPU_PWR_LVL) { 148 num_nodes_at_next_lvl = 0U; 149 /* 150 * For each entry (parent node) at this level in the plat_array: 151 * - Find the number of children 152 * - Allocate a node in a power domain array for each child 153 * - Set the parent of the child to the parent_node_index - 1 154 * - Increment parent_node_index to point to the next parent 155 * - Accumulate the number of children at next level. 156 */ 157 for (i = 0U; i < num_nodes_at_lvl; i++) { 158 assert(parent_node_index <= 159 PSCI_NUM_NON_CPU_PWR_DOMAINS); 160 num_children = topology[parent_node_index]; 161 162 for (j = node_index; 163 j < (node_index + num_children); j++) 164 psci_init_pwr_domain_node((uint16_t)j, 165 parent_node_index - 1U, 166 (unsigned char)level); 167 168 node_index = j; 169 num_nodes_at_next_lvl += num_children; 170 parent_node_index++; 171 } 172 173 num_nodes_at_lvl = num_nodes_at_next_lvl; 174 level--; 175 176 /* Reset the index for the cpu power domain array */ 177 if (level == (int) PSCI_CPU_PWR_LVL) 178 node_index = 0; 179 } 180 181 /* Validate the sanity of array exported by the platform */ 182 assert(j <= PLATFORM_CORE_COUNT); 183 return j; 184 } 185 186 /******************************************************************************* 187 * This function does the architectural setup and takes the warm boot 188 * entry-point `mailbox_ep` as an argument. The function also initializes the 189 * power domain topology tree by querying the platform. The power domain nodes 190 * higher than the CPU are populated in the array psci_non_cpu_pd_nodes[] and 191 * the CPU power domains are populated in psci_cpu_pd_nodes[]. The platform 192 * exports its static topology map through the 193 * populate_power_domain_topology_tree() API. The algorithm populates the 194 * psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this 195 * topology map. On a platform that implements two clusters of 2 cpus each, 196 * and supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would 197 * look like this: 198 * 199 * --------------------------------------------------- 200 * | system node | cluster 0 node | cluster 1 node | 201 * --------------------------------------------------- 202 * 203 * And populated psci_cpu_pd_nodes would look like this : 204 * <- cpus cluster0 -><- cpus cluster1 -> 205 * ------------------------------------------------ 206 * | CPU 0 | CPU 1 | CPU 2 | CPU 3 | 207 * ------------------------------------------------ 208 ******************************************************************************/ 209 int __init psci_setup(const psci_lib_args_t *lib_args) 210 { 211 const unsigned char *topology_tree; 212 unsigned int cpu_idx = plat_my_core_pos(); 213 214 assert(VERIFY_PSCI_LIB_ARGS_V1(lib_args)); 215 216 /* Do the Architectural initialization */ 217 psci_arch_setup(); 218 219 /* Query the topology map from the platform */ 220 topology_tree = plat_get_power_domain_tree_desc(); 221 222 /* Populate the power domain arrays using the platform topology map */ 223 psci_plat_core_count = populate_power_domain_tree(topology_tree); 224 225 /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */ 226 psci_update_pwrlvl_limits(); 227 228 /* Initialise the warmboot entrypoints */ 229 populate_cpu_data(); 230 231 /* Populate the mpidr field of cpu node for this CPU */ 232 psci_cpu_pd_nodes[cpu_idx].mpidr = 233 read_mpidr() & MPIDR_AFFINITY_MASK; 234 235 psci_init_req_local_pwr_states(); 236 237 /* 238 * Set the requested and target state of this CPU and all the higher 239 * power domain levels for this CPU to run. 240 */ 241 psci_set_pwr_domains_to_run(cpu_idx, PLAT_MAX_PWR_LVL); 242 243 (void) plat_setup_psci_ops((uintptr_t)lib_args->mailbox_ep, 244 &psci_plat_pm_ops); 245 assert(psci_plat_pm_ops != NULL); 246 247 /* 248 * Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs 249 * during warm boot, possibly before data cache is enabled. 250 */ 251 psci_flush_dcache_range((uintptr_t)&psci_plat_pm_ops, 252 sizeof(psci_plat_pm_ops)); 253 254 /* Initialize the psci capability */ 255 psci_caps = PSCI_GENERIC_CAP; 256 257 if (psci_plat_pm_ops->pwr_domain_off != NULL) { 258 psci_caps |= define_psci_cap(PSCI_CPU_OFF); 259 } 260 if ((psci_plat_pm_ops->pwr_domain_on != NULL) && 261 (psci_plat_pm_ops->pwr_domain_on_finish != NULL)) { 262 psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64); 263 } 264 if ((psci_plat_pm_ops->pwr_domain_suspend != NULL) && 265 (psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)) { 266 if (psci_plat_pm_ops->validate_power_state != NULL) { 267 psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64); 268 } 269 if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL) { 270 psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64); 271 } 272 #if PSCI_OS_INIT_MODE 273 psci_caps |= define_psci_cap(PSCI_SET_SUSPEND_MODE); 274 #endif 275 } 276 if (psci_plat_pm_ops->system_off != NULL) { 277 psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF); 278 } 279 if (psci_plat_pm_ops->system_reset != NULL) { 280 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET); 281 } 282 if (psci_plat_pm_ops->get_node_hw_state != NULL) { 283 psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64); 284 } 285 if ((psci_plat_pm_ops->read_mem_protect != NULL) && 286 (psci_plat_pm_ops->write_mem_protect != NULL)) { 287 psci_caps |= define_psci_cap(PSCI_MEM_PROTECT); 288 } 289 if (psci_plat_pm_ops->mem_protect_chk != NULL) { 290 psci_caps |= define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64); 291 } 292 if (psci_plat_pm_ops->system_reset2 != NULL) { 293 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64); 294 } 295 #if ENABLE_PSCI_STAT 296 psci_caps |= define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64); 297 psci_caps |= define_psci_cap(PSCI_STAT_COUNT_AARCH64); 298 #endif 299 300 return 0; 301 } 302 303 /******************************************************************************* 304 * This duplicates what the primary cpu did after a cold boot in BL1. The same 305 * needs to be done when a cpu is hotplugged in. This function could also over- 306 * ride any EL3 setup done by BL1 as this code resides in rw memory. 307 ******************************************************************************/ 308 void psci_arch_setup(void) 309 { 310 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER) 311 /* Program the counter frequency */ 312 write_cntfrq_el0(plat_get_syscnt_freq2()); 313 #endif 314 315 /* Initialize the cpu_ops pointer. */ 316 init_cpu_ops(); 317 318 /* Having initialized cpu_ops, we can now print errata status */ 319 print_errata_status(); 320 321 } 322 323 /****************************************************************************** 324 * PSCI Library interface to initialize the cpu context for the next non 325 * secure image during cold boot. The relevant registers in the cpu context 326 * need to be retrieved and programmed on return from this interface. 327 *****************************************************************************/ 328 void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info) 329 { 330 assert(GET_SECURITY_STATE(next_image_info->h.attr) == NON_SECURE); 331 cm_init_my_context(next_image_info); 332 cm_prepare_el3_exit(NON_SECURE); 333 } 334