| e73d9d0f | 24-Jul-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge "refactor(aarch64): remove `FEAT_BTI` architecture check" into integration |
| 37596fcb | 25-Nov-2020 |
Daniel Boulby <danielboulby@arm.com> |
fix(sdei): set SPSR for SDEI based on TakeException
The SDEI specification now says that during an SDEI
event handler dispatch the SPSR should be set according
to the TakeException() pseudocode func
fix(sdei): set SPSR for SDEI based on TakeException
The SDEI specification now says that during an SDEI
event handler dispatch the SPSR should be set according
to the TakeException() pseudocode function defined in
the Arm Architecture Reference Manual. This patch sets
the SPSR according to the function given in
ARM DDI 0487F.c page J1-7635
Change-Id: Id2f8f2464fd69c701d81626162827e5c4449b658
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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|
| 68ac5ed0 | 08-Jul-2021 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon e
fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
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|
| 9aedca02 | 14-Dec-2020 |
Samuel Holland <samuel@sholland.org> |
feat(bl_common): import BL_NOBITS_{BASE,END} when defined
If SEPARATE_NOBITS_REGION is enabled, the platform may need to map
memory specifically for that region. Import the symbols from the linker
s
feat(bl_common): import BL_NOBITS_{BASE,END} when defined
If SEPARATE_NOBITS_REGION is enabled, the platform may need to map
memory specifically for that region. Import the symbols from the linker
script to allow the platform to do so.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iaec4dee94a6735b22f58f7b61f18d53e7bc6ca8d
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|
| fd1360a3 | 20-Jul-2021 |
Pali Rohár <pali@kernel.org> |
feat(common/debug): add new macro ERROR_NL() to print just a newline
Existing macro ERROR() prints string "ERROR" followed by string
specified by caller. Therefore via this existing macro it is not
feat(common/debug): add new macro ERROR_NL() to print just a newline
Existing macro ERROR() prints string "ERROR" followed by string
specified by caller. Therefore via this existing macro it is not
possible to end incomplete / existing line by a newline character.
This change adds a new macro ERROR_NL() which prints just a newline
character without any prefix. Implementation of this macro is done via a
new function tf_log_newline() which based on supplied log level either
return or print newline character.
If needed in future based on this tf_log_newline() function can be
defined also macros for other log levels.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I05414ca177f94cdc0f6077394d9c4af4a4382306
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|
| 586aafa3 | 19-Jul-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1791573" into integration |
| 33e3e925 | 03-May-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
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|
| 9a9ea829 | 17-Jul-2020 |
Lionel Debieve <lionel.debieve@st.com> |
feat(io_mtd): offset management for FIP usage
A new seek handler is also created. It will be used for NAND to add an
extra offset in case of bad blocks, when FIP is used.
Change-Id: I03fb1588b44029
feat(io_mtd): offset management for FIP usage
A new seek handler is also created. It will be used for NAND to add an
extra offset in case of bad blocks, when FIP is used.
Change-Id: I03fb1588b44029db50583c0b2e7af7a1e88a5a7a
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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|
| bc3eebb2 | 05-Aug-2020 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(nand): count bad blocks before a given offset
In case of FIP, the offsets given in the FIP header are relative.
If bad blocks are found between the FIP base address and this offset,
the offset
feat(nand): count bad blocks before a given offset
In case of FIP, the offsets given in the FIP header are relative.
If bad blocks are found between the FIP base address and this offset,
the offset should be updated, taking care of the bad blocks.
Change-Id: I96fefabb583b3d030ab05191bae7d45cfeefe341
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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|
| 52698a62 | 09-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(mpam): remove unused function declaration
Change-Id: Ia660b6554fe4544effd1810e1aca202f95e3c447
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> |
| c1c14b34 | 30-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1" into integration |
| 81a8b2da | 30-Jun-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(sve): enable SVE for the secure world" into integration |
| 204fd991 | 29-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "errata: workaround for Cortex A77 errata 1791578" into integration |
| 7285fd5f | 10-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The un
feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The underlying changes for enabling PIE in aarch32 is submitted in
commit 4324a14bf
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
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|
| 0c5e7d1c | 22-Mar-2021 |
Max Shvetsov <maksims.svecovs@arm.com> |
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is conf
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
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|
| 1a691455 | 30-Apr-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/603e3733492bde1625aa8780
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
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|
| 3f0bec7c | 03-May-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
h
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib4b963144f880002de308def12744b982d3df868
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|
| 64b8db7e | 22-Jun-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "refactor(dt-bindings): align irq bindings with kernel" into integration |
| 4429b471 | 09-Mar-2021 |
Chris Kay <chris.kay@arm.com> |
refactor(aarch64): remove `FEAT_BTI` architecture check
BTI instructions are a part of the NOP space in earlier architecture
versions, so it's not inherently incorrect to enable BTI code
or instruct
refactor(aarch64): remove `FEAT_BTI` architecture check
BTI instructions are a part of the NOP space in earlier architecture
versions, so it's not inherently incorrect to enable BTI code
or instructions even if the target architecture does not support them.
This change reduces our reliance on architecture versions when checking
for features.
Change-Id: I79f884eec3d65978c61e72e4268021040fd6c96e
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 967344b5 | 18-Jun-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(spmd): add support for FFA_SPM_ID_GET" into integration |
| 2a008779 | 16-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "soc_id" into integration
* changes:
refactor(plat/nvidia): use SOC_ID defines
refactor(plat/mediatek): use SOC_ID defines
refactor(plat/arm): use SOC_ID defines
fea
Merge changes from topic "soc_id" into integration
* changes:
refactor(plat/nvidia): use SOC_ID defines
refactor(plat/mediatek): use SOC_ID defines
refactor(plat/arm): use SOC_ID defines
feat(plat/st): implement platform functions for SMCCC_ARCH_SOC_ID
refactor(plat/st): export functions to get SoC information
feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID
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|
| f1b6b014 | 25-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(dt-bindings): align irq bindings with kernel
The arm-gic.h was a concatenation of arm-gic.h and irq.h from Linux.
Just copy the 2 files here. They both have MIT license which is accepted
in
refactor(dt-bindings): align irq bindings with kernel
The arm-gic.h was a concatenation of arm-gic.h and irq.h from Linux.
Just copy the 2 files here. They both have MIT license which is accepted
in TF-A.
With this alignment, a new macro is added (GIC_CPU_MASK_SIMPLE).
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ib45174f35f1796ebb7f34af861b59810cfb808b0
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|
| 66bf006e | 08-Jun-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(security): Set MDCR_EL3.MCCD bit" into integration |
| b39a1308 | 07-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I85a87dc9,If75df769,I55b0c910 into integration
* changes:
feat(plat/st): add STM32MP_EMMC_BOOT option
feat(drivers/st): manage boot part in io_mmc
feat(drivers/mmc): boot partiti
Merge changes I85a87dc9,If75df769,I55b0c910 into integration
* changes:
feat(plat/st): add STM32MP_EMMC_BOOT option
feat(drivers/st): manage boot part in io_mmc
feat(drivers/mmc): boot partition read support
show more ...
|
| 076bb38d | 07-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(plat/marvell/a3720/uart): fix UART parent clock rate determination" into integration |