feat(lfa): implement LFA_GET_INVENTORY SMC

This implementation primarily retrieves activation-related flags for
a given fw_seq_id, including whether the firmware is activation
capable, whether an up

feat(lfa): implement LFA_GET_INVENTORY SMC

This implementation primarily retrieves activation-related flags for
a given fw_seq_id, including whether the firmware is activation
capable, whether an update is pending activation, whether it resets
the CPU during activation, whether CPU rendezvous is required, and the
firmware's UUID.
To support this, a platform API is called to determine whether an
update is available for the specified fw_seq_id, indicating its
pending activation status.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6e702a8b313386f5668027386845ff2dae9328e7

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feat(lfa): implement LFA_GET_INFO SMC and integrate LFA build

Implement the LFA_GET_INFO SMC handler, which retrieves the
number of supported firmware components and performs initial
setup via the p

feat(lfa): implement LFA_GET_INFO SMC and integrate LFA build

Implement the LFA_GET_INFO SMC handler, which retrieves the
number of supported firmware components and performs initial
setup via the platform APIs. This forms the entry point for
LFA usage and makes component metadata available for later use.

Update the build system to include LFA sources.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I4016615a88706972eff6ea5777dda6d5a3a04074

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feat(rmm): add placeholder activator callbacks for LFA

Introduce the RMM component's activator structure for use in
LFA. The 'prime' and 'activate' callbacks currently return
LFA_WRONG_STATE as plac

feat(rmm): add placeholder activator callbacks for LFA

Introduce the RMM component's activator structure for use in
LFA. The 'prime' and 'activate' callbacks currently return
LFA_WRONG_STATE as placeholders.

These functions will be implemented in subsequent patches in
this series to support actual RMM component activation logic.

Change-Id: I899ff51e4065887b7b4bbfbaa827322c51cd215c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(bl31): add placeholder activator implementation for LFA

Introduce the BL31 component's activator structure with stub
implementations for the 'prime' and 'activate' callbacks.

Both callbacks cu

feat(bl31): add placeholder activator implementation for LFA

Introduce the BL31 component's activator structure with stub
implementations for the 'prime' and 'activate' callbacks.

Both callbacks currently return LFA_WRONG_STATE, indicating that
activation is not supported or allowed from BL31 in this context.

This activator is registered via get_bl31_activator(), allowing
the platform layer to wire it into the LFA framework.

Change-Id: I4279996b218d558a45cd99d5840f0e9f8ee97f90
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(lfa): add activation handler interface for component activation

Introduce `lfa_component_desc.h` defining structures and function
types to support component activation in LFA.

Includes:
- lfa_

feat(lfa): add activation handler interface for component activation

Introduce `lfa_component_desc.h` defining structures and function
types to support component activation in LFA.

Includes:
- lfa_component_status: to track per-component activation state
- lfa_component_ops: function table for prime and activate callbacks

The platform layer uses this interface to register component-specific
callbacks during initialization. These callbacks are implemented in
the component layer, and invoked by the LFA service to coordinate
activation by passing lfa_component_status details.

Change-Id: I141d49679bad3f134a2c5360342331604d2002f8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(lfa): create LFA SMC handler template

As per the specification v1.0[1], added all Live Firmware Activation
(LFA) SMCs, including their Function IDs (FIDs) and associated error
codes.
A dummy ha

feat(lfa): create LFA SMC handler template

As per the specification v1.0[1], added all Live Firmware Activation
(LFA) SMCs, including their Function IDs (FIDs) and associated error
codes.
A dummy handler function has been created as a template. Subsequent
patches will implement the handling of these SMCs.

[1]: https://developer.arm.com/documentation/den0147/latest/

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I5d6500dcff35aa4a438cd5f97f349cd57406ddce

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fix(drtm): set correct max region mask for DMA protection to 0xFFFF

Update `ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK` from `0xF` to
`0xFFFF` to correctly reflect the maximum number of supported D

fix(drtm): set correct max region mask for DMA protection to 0xFFFF

Update `ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK` from `0xF` to
`0xFFFF` to correctly reflect the maximum number of supported DMA
protection regions, as per the expected DRTM capability encoding.

The previous 4-bit mask limited the range to 16 regions, which is
insufficient and incorrect based on the spec's intention. This fix
extends the bitmask to 16 bits, allowing up to 65,535 regions if
supported in future implementations.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2531706f4b75125b510413870dfd4b1804e5adb6

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feat(smcc): introduce a new vendor_el3 service for ACS SMC handler

In preparation to add support for the Architecture Compliance Suite
SMC services, reserve a SMC ID and introduce a handler function

feat(smcc): introduce a new vendor_el3 service for ACS SMC handler

In preparation to add support for the Architecture Compliance Suite
SMC services, reserve a SMC ID and introduce a handler function.
Currently, an empty placeholder function is added and future support
will be introduced for the handler support.

More info on System ACS, please refer below link,
https://developer.arm.com/Architectures/Architectural%20Compliance%20Suite

Signed-off-by: Nandan J <Nandan.J@arm.com>
Change-Id: Ib13ccae9d3829e3dcd1cd33c4a7f27efe1436d03

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Merge "feat(spe): add support for FEAT_SPE_FDS" into integration

Merge changes I0b0443d5,Ic454a87a into integration

* changes:
fix(gic): quote the correct flag on error
feat(lib): add a generic EXTRACT macro

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY
feat(cpufeat): add support for PMUv3p9

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feat(lib): add a generic EXTRACT macro

The EXTRACT macro is useful to extract a named field from a numeric
value, usually a register. It is functionally identical to the `ubfx`
instruction and uses

feat(lib): add a generic EXTRACT macro

The EXTRACT macro is useful to extract a named field from a numeric
value, usually a register. It is functionally identical to the `ubfx`
instruction and uses the same #defines (REG_FIELD_SHIFT and
REG_FIELD_WIDTH).

This is the same macro that we use in tftf. It works well there and is
quite useful for manipulating register fields concisely.

This macro replaces the EXTRACT_FIELD macro. Their function is
identical, however, EXTRACT allows for easier interoperation with the
`ubfx` instruction, makes code more similar to tftf, and is more
concise.

Change-Id: Ic454a87af5e5fac108c7b7cb6b6804ec65a8d0e8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by

feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by: James Clark <james.clark2@arm.com>

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feat(trp): test el3-rmm ide km interface

This patch introduces test functions to the Test Realm Payload (TRP)
for performing basic sanity checks on the RMM-EL3 IDE KM support added
to EL3.

The prim

feat(trp): test el3-rmm ide km interface

This patch introduces test functions to the Test Realm Payload (TRP)
for performing basic sanity checks on the RMM-EL3 IDE KM support added
to EL3.

The primary goal of this patch is to only to verify the basic
functionality and ensure the implemented functions return the
correct return values.

The test uses random values for the ecam address, rootport ID,
IDE stream info, keys, and IV values.

Change-Id: Icf47627da9a6a7dd0d6e40e20ac94cc977072177
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(rmmd): el3-rmm ide key management interface

Patch introduces the EL3-RMM SMC Interface for Root Port
Key management as per RFC discussed here:
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM

feat(rmmd): el3-rmm ide key management interface

Patch introduces the EL3-RMM SMC Interface for Root Port
Key management as per RFC discussed here:
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface

Three IDE Key management smc calls have been added:
- RMM_IDE_KEY_PROG()
- RMM_IDE_KEY_SET_GO()
- RMM_IDE_KEY_SET_STOP()
- RMM_IDE_KM_PULL_RESPONSE()

Due to the absence of root port support in FVP, we are
currently adding placeholders in this patch for the platform
APIs to return success irrespective of the arguments being passed
by the caller(Realms). The SMCs are guarded by
`RMMD_ENABLE_IDE_KEY_PROG` build flag and is disabled by default.
We expect that once the SMCs are stabilized, this build flag will
not be required anymore.

Change-Id: I9411eb7787dac2a207bd14710d251503bd9626ce
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(smccc): properly set RAS feature bit

The SCR_EL3.TERR bit controls trapping accesses to the RAS CPU system
registers, like ERRIDR_EL1. Those are part of RAS CPU extension, and
exist and can be a

fix(smccc): properly set RAS feature bit

The SCR_EL3.TERR bit controls trapping accesses to the RAS CPU system
registers, like ERRIDR_EL1. Those are part of RAS CPU extension, and
exist and can be accessed independently of the rest of the system's RAS
implementation status, BL31's RAS handling capabilities, or the way RAS
errors are routed by the firmware (FFH vs. KFH handling).
Tie the SCR_EL3.TERR bit to the right build symbol, since TF-A's
capability to handle RAS errors has nothing to do with lower EL's
accesses to those CPU system registers.

Change-Id: I4f06f915c0815c80058ec365139a8d818ba85721
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY

FEAT_TWED (Delayed Trapping of WFE) is an ARMv8.6 feature that is
advertised in the ID_AA64MMFR1_EL1 ID register and controlled by a bit
in th

feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY

FEAT_TWED (Delayed Trapping of WFE) is an ARMv8.6 feature that is
advertised in the ID_AA64MMFR1_EL1 ID register and controlled by a bit
in the SCR_EL3 register.

On cores implementing that feature we should announce it in the
ARCH_FEATURE_AVAILABILITY SMCCC call, so that users of that interface
can correctly assess the availability of the delayed trap.

Change-Id: I2b185f7eb9d58e45472983204db0305511372477
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(cpufeat): add support for PMUv3p9

Armv8.9 introduced the FEAT_PMUV3P9 extension, which allows finer
grained control over EL0 usage of PMU registers. This is controlled by
the new PMUACR_EL1 sys

feat(cpufeat): add support for PMUv3p9

Armv8.9 introduced the FEAT_PMUV3P9 extension, which allows finer
grained control over EL0 usage of PMU registers. This is controlled by
the new PMUACR_EL1 system register, access to which is guarded by the
MDCR_EL3.EnPM2 bit. We should set this bit to avoid a trap into EL3 when
lower ELs access this register.

Add the required bits and pieces to make this feature usable:
- Add the CPUID and MDCR_EL3 bit definitions associated with
FEAT_PMUV3P9.
- Extend the existing PMU feature check to allow v9 now as well. This
is fine since we don't context switch PMU registers at all, so we
don't need to do much except to flip the MDCR bit:
- Set the EnPM2 bit in pmuv3_enable, so the feature is usuable in
non-secure world (and there only).
- Handle the MDCR bit for the ARCH_FEATURE_AVAILABILITY feature.

Please note that MDCR_EL3.EnPM2 guards other system registers as well,
for other PMU related new architecture features.

Change-Id: I288ca15f5c9efd336c64477d1c6fe9543613e238
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(spmd): check pwr mgmt status for SPMC framework response

The direct message response received by the SPMD upon a CPU_OFF power
management operation must be a framework message. If message indica

fix(spmd): check pwr mgmt status for SPMC framework response

The direct message response received by the SPMD upon a CPU_OFF power
management operation must be a framework message. If message indicates
SPMC denied the CPU_OFF operation, SPMD shall panic.

However, if SPMC does not support receiving power management
related framework messages from SPMD, it will return FFA_ERROR.
In such case, SPMD takes an implementation defined choice to ignore the
the FFA_ERROR and proceed with power management operation.

Change-Id: I18b9ee3fb8fd605bcd4aaa6802c969e9d36ccbe1
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(rme): add SMMU and PCIe information to Boot manifest

- Define information structures for SMMU, root complex,
root port and BDF mappings.
- Add entries for SMMU and PCIe root complexes to Boot

feat(rme): add SMMU and PCIe information to Boot manifest

- Define information structures for SMMU, root complex,
root port and BDF mappings.
- Add entries for SMMU and PCIe root complexes to Boot manifest.
- Update RMMD_MANIFEST_VERSION_MINOR from 4 to 5.

Change-Id: I0a76dc18edbaaff40116f376aeb56c750d57c7c1
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge changes from topic "mec" into integration

* changes:
feat(qemu): add plat_rmmd_mecid_key_update()
feat(rmmd): add RMM_MECID_KEY_UPDATE call

feat(rmmd): add RMM_MECID_KEY_UPDATE call

With this addition, TF-A now has an SMC call to handle the
update of MEC keys associated to MECIDs.

The behavior of this newly added call is empty for now

feat(rmmd): add RMM_MECID_KEY_UPDATE call

With this addition, TF-A now has an SMC call to handle the
update of MEC keys associated to MECIDs.

The behavior of this newly added call is empty for now until an
implementation for the MPE (Memory Protection Engine) driver is
available. Only parameter sanitization has been implemented.

Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I2a969310b47e8c6da1817a79be0cd56158c6efc3

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Merge changes from topic "mb/drtm" into integration

* changes:
feat(drtm): validate launch features in DRTM parameters
feat(lib): add EXTRACT_FIELD macro for field extraction

Merge "feat(rmmd): add FEAT_MEC support" into integration

feat(rmmd): add FEAT_MEC support

This patch provides architectural support for further use of
Memory Encryption Contexts (MEC) by declaring the necessary
registers, bits, masks, helpers and values a

feat(rmmd): add FEAT_MEC support

This patch provides architectural support for further use of
Memory Encryption Contexts (MEC) by declaring the necessary
registers, bits, masks, helpers and values and modifying the
necessary registers to enable FEAT_MEC.

Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I670dbfcef46e131dcbf3a0b927467ebf6f438fa4

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