1# 2# Copyright (c) 2016-2024, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33RESET_TO_BL2 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when RESET_TO_BL2 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Include SVE registers in cpu context 67CTX_INCLUDE_SVE_REGS := 0 68 69# Debug build 70DEBUG := 0 71 72# By default disable authenticated decryption support. 73DECRYPTION_SUPPORT := none 74 75# Build platform 76DEFAULT_PLAT := fvp 77 78# Disable the generation of the binary image (ELF only). 79DISABLE_BIN_GENERATION := 0 80 81# Enable capability to disable authentication dynamically. Only meant for 82# development platforms. 83DYN_DISABLE_AUTH := 0 84 85# Enable the Maximum Power Mitigation Mechanism on supporting cores. 86ENABLE_MPMM := 0 87 88# Enable MPMM configuration via FCONF. 89ENABLE_MPMM_FCONF := 0 90 91# Flag to Enable Position Independant support (PIE) 92ENABLE_PIE := 0 93 94# Flag to enable Performance Measurement Framework 95ENABLE_PMF := 0 96 97# Flag to enable PSCI STATs functionality 98ENABLE_PSCI_STAT := 0 99 100# Flag to enable runtime instrumentation using PMF 101ENABLE_RUNTIME_INSTRUMENTATION := 0 102 103# Flag to enable stack corruption protection 104ENABLE_STACK_PROTECTOR := 0 105 106# Flag to enable exception handling in EL3 107EL3_EXCEPTION_HANDLING := 0 108 109# By default BL31 encryption disabled 110ENCRYPT_BL31 := 0 111 112# By default BL32 encryption disabled 113ENCRYPT_BL32 := 0 114 115# Default dummy firmware encryption key 116ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 117 118# Default dummy nonce for firmware encryption 119ENC_NONCE := 1234567890abcdef12345678 120 121# Build flag to treat usage of deprecated platform and framework APIs as error. 122ERROR_DEPRECATED := 0 123 124# Fault injection support 125FAULT_INJECTION_SUPPORT := 0 126 127# Flag to enable architectural features detection mechanism 128FEATURE_DETECTION := 0 129 130# Byte alignment that each component in FIP is aligned to 131FIP_ALIGN := 0 132 133# Default FIP file name 134FIP_NAME := fip.bin 135 136# Default FWU_FIP file name 137FWU_FIP_NAME := fwu_fip.bin 138 139# By default firmware encryption with SSK 140FW_ENC_STATUS := 0 141 142# For Chain of Trust 143GENERATE_COT := 0 144 145# Default number of 512 blocks per bitlock 146RME_GPT_BITLOCK_BLOCK := 1 147 148# Default maximum size of GPT contiguous block 149RME_GPT_MAX_BLOCK := 512 150 151# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 152# default, they are for Secure EL1. 153GICV2_G0_FOR_EL3 := 0 154 155# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 156# by lower ELs. 157HANDLE_EA_EL3_FIRST_NS := 0 158 159# Enable Handoff protocol using transfer lists 160TRANSFER_LIST := 0 161 162# Enable HOB list to generate boot information 163HOB_LIST := 0 164 165# Enables support for the gcc compiler option "-mharden-sls=all". 166# By default, disables all SLS hardening. 167HARDEN_SLS := 0 168 169# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 170# The default value is sha256. 171HASH_ALG := sha256 172 173# Whether system coherency is managed in hardware, without explicit software 174# operations. 175HW_ASSISTED_COHERENCY := 0 176 177# Flag to enable trapping of implementation defined sytem registers 178IMPDEF_SYSREG_TRAP := 0 179 180# Set the default algorithm for the generation of Trusted Board Boot keys 181KEY_ALG := rsa 182 183# Set the default key size in case KEY_ALG is rsa 184ifeq ($(KEY_ALG),rsa) 185KEY_SIZE := 2048 186endif 187 188# Option to build TF with Measured Boot support 189MEASURED_BOOT := 0 190 191# Option to enable the DICE Protection Environmnet as a Measured Boot backend 192DICE_PROTECTION_ENVIRONMENT :=0 193 194# NS timer register save and restore 195NS_TIMER_SWITCH := 0 196 197# Include lib/libc in the final image 198OVERRIDE_LIBC := 0 199 200# Build PL011 UART driver in minimal generic UART mode 201PL011_GENERIC_UART := 0 202 203# By default, consider that the platform's reset address is not programmable. 204# The platform Makefile is free to override this value. 205PROGRAMMABLE_RESET_ADDRESS := 0 206 207# Flag used to choose the power state format: Extended State-ID or Original 208PSCI_EXTENDED_STATE_ID := 0 209 210# Enable PSCI OS-initiated mode support 211PSCI_OS_INIT_MODE := 0 212 213# SMCCC_ARCH_FEATURE_AVAILABILITY support 214ARCH_FEATURE_AVAILABILITY := 0 215 216# By default, BL1 acts as the reset handler, not BL31 217RESET_TO_BL31 := 0 218 219# For Chain of Trust 220SAVE_KEYS := 0 221 222# Software Delegated Exception support 223SDEI_SUPPORT := 0 224 225# True Random Number firmware Interface support 226TRNG_SUPPORT := 0 227 228# Check to see if Errata ABI is supported 229ERRATA_ABI_SUPPORT := 0 230 231# Check to enable Errata ABI for platforms with non-arm interconnect 232ERRATA_NON_ARM_INTERCONNECT := 0 233 234# SMCCC PCI support 235SMC_PCI_SUPPORT := 0 236 237# Whether code and read-only data should be put on separate memory pages. The 238# platform Makefile is free to override this value. 239SEPARATE_CODE_AND_RODATA := 0 240 241# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 242# separate memory region, which may be discontiguous from the rest of BL31. 243SEPARATE_NOBITS_REGION := 0 244 245# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 246# region, platform Makefile is free to override this value. 247SEPARATE_BL2_NOLOAD_REGION := 0 248 249# Put RW DATA sections (.rwdata) in a separate memory region, which may be 250# discontiguous from the rest of BL31. 251SEPARATE_RWDATA_REGION := 0 252 253# Put SIMD context data structures in a separate memory region. Platforms 254# have the choice to put it outside of default BSS region of EL3 firmware. 255SEPARATE_SIMD_SECTION := 0 256 257# If the BL31 image initialisation code is recalimed after use for the secondary 258# cores stack 259RECLAIM_INIT_CODE := 0 260 261# SPD choice 262SPD := none 263 264# Enable the Management Mode (MM)-based Secure Partition Manager implementation 265SPM_MM := 0 266 267# Use the FF-A SPMC implementation in EL3. 268SPMC_AT_EL3 := 0 269 270# Enable SEL0 SP when SPMC is enabled at EL3 271SPMC_AT_EL3_SEL0_SP :=0 272 273# Use SPM at S-EL2 as a default config for SPMD 274SPMD_SPM_AT_SEL2 := 1 275 276# Flag to introduce an infinite loop in BL1 just before it exits into the next 277# image. This is meant to help debugging the post-BL2 phase. 278SPIN_ON_BL1_EXIT := 0 279 280# Flags to build TF with Trusted Boot support 281TRUSTED_BOARD_BOOT := 0 282 283# Build option to choose whether Trusted Firmware uses Coherent memory or not. 284USE_COHERENT_MEM := 1 285 286# Build option to add debugfs support 287USE_DEBUGFS := 0 288 289# Build option to fconf based io 290ARM_IO_IN_DTB := 0 291 292# Build option to support SDEI through fconf 293SDEI_IN_FCONF := 0 294 295# Build option to support Secure Interrupt descriptors through fconf 296SEC_INT_DESC_IN_FCONF := 0 297 298# Build option to choose whether Trusted Firmware uses library at ROM 299USE_ROMLIB := 0 300 301# Build option to choose whether the xlat tables of BL images can be read-only. 302# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 303# which is the per BL-image option that actually enables the read-only tables 304# API. The reason for having this additional option is to have a common high 305# level makefile where we can check for incompatible features/build options. 306ALLOW_RO_XLAT_TABLES := 0 307 308# Chain of trust. 309COT := tbbr 310 311# Use tbbr_oid.h instead of platform_oid.h 312USE_TBBR_DEFS := 1 313 314# Whether to enable D-Cache early during warm boot. This is usually 315# applicable for platforms wherein interconnect programming is not 316# required to enable cache coherency after warm reset (eg: single cluster 317# platforms). 318WARMBOOT_ENABLE_DCACHE_EARLY := 0 319 320# Default SVE vector length to maximum architected value 321SVE_VECTOR_LEN := 2048 322 323SANITIZE_UB := off 324 325# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 326# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 327# Default: disabled 328USE_SPINLOCK_CAS := 0 329 330# Enable Link Time Optimization 331ENABLE_LTO := 0 332 333# This option will include EL2 registers in cpu context save and restore during 334# EL2 firmware entry/exit. Internal flag not meant for direct setting. 335# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 336# CTX_INCLUDE_EL2_REGS. 337CTX_INCLUDE_EL2_REGS := 0 338 339# Enable Memory tag extension which is supported for architecture greater 340# than Armv8.5-A 341# By default it is set to "no" 342SUPPORT_STACK_MEMTAG := no 343 344# Select workaround for AT speculative behaviour. 345ERRATA_SPECULATIVE_AT := 0 346 347# Trap RAS error record access from Non secure 348RAS_TRAP_NS_ERR_REC_ACCESS := 0 349 350# Build option to create cot descriptors using fconf 351COT_DESC_IN_DTB := 0 352 353# Build option to provide OpenSSL directory path 354OPENSSL_DIR := /usr 355 356# Select the openssl binary provided in OPENSSL_DIR variable 357ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 358 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 359else 360 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 361endif 362 363# Build option to use the SP804 timer instead of the generic one 364USE_SP804_TIMER := 0 365 366# Build option to define number of firmware banks, used in firmware update 367# metadata structure. 368NR_OF_FW_BANKS := 2 369 370# Build option to define number of images in firmware bank, used in firmware 371# update metadata structure. 372NR_OF_IMAGES_IN_FW_BANK := 1 373 374# Disable Firmware update support by default 375PSA_FWU_SUPPORT := 0 376 377# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT 378# is enabled. 379ifeq ($(PSA_FWU_SUPPORT),1) 380PSA_FWU_METADATA_FW_STORE_DESC := 1 381else 382PSA_FWU_METADATA_FW_STORE_DESC := 0 383endif 384 385# Dynamic Root of Trust for Measurement support 386DRTM_SUPPORT := 0 387 388# Check platform if cache management operations should be performed. 389# Disabled by default. 390CONDITIONAL_CMO := 0 391 392# By default, disable SPMD Logical partitions 393ENABLE_SPMD_LP := 0 394 395# By default, disable PSA crypto (use MbedTLS legacy crypto API). 396PSA_CRYPTO := 0 397 398# getc() support from the console(s). 399# Disabled by default because it constitutes an attack vector into TF-A. It 400# should only be enabled if there is a use case for it. 401ENABLE_CONSOLE_GETC := 0 402 403# Build option to disable EL2 when it is not used. 404# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 405# functions must be enabled by platforms if they require it. 406# Disabled by default. 407INIT_UNUSED_NS_EL2 := 0 408 409# Disable including MPAM EL2 registers in context by default since currently 410# it's only enabled for NS world 411CTX_INCLUDE_MPAM_REGS := 0 412 413# Enable context memory usage reporting during BL31 setup. 414PLATFORM_REPORT_CTX_MEM_USE := 0 415 416# Enable early console 417EARLY_CONSOLE := 0 418 419# Allow platforms to save/restore DSU PMU registers over a power cycle. 420# Disabled by default and must be enabled by individual platforms. 421PRESERVE_DSU_PMU_REGS := 0 422 423# Enable RMMD to forward attestation requests from RMM to EL3. 424RMMD_ENABLE_EL3_TOKEN_SIGN := 0 425