| 5486a965 | 21-Oct-2016 |
Soby Mathew <soby.mathew@arm.com> |
Allow ARM Standard platforms to dynamically define PSCI capability
The capabilities exposed by the PSCI generic layer depends on the hooks populated by the platform in `plat_arm_psci_pm_ops`. Curren
Allow ARM Standard platforms to dynamically define PSCI capability
The capabilities exposed by the PSCI generic layer depends on the hooks populated by the platform in `plat_arm_psci_pm_ops`. Currently ARM Standard platforms statically define this structure. However, some platforms may want to modify the hooks at runtime before registering them with the generic layer.
This patch introduces a new ARM platform layer API `plat_arm_psci_override_pm_ops` which allows the platform to probe the power controller and modify `plat_arm_psci_pm_ops` if required. Consequently, 'plat_arm_psci_pm_ops' is no longer qualified as `const` on ARM Standard platforms.
Change-Id: I7dbb44b7bd36c20ec14ded5ee45a96816ca2ab9d Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| f10796a0 | 19-Sep-2016 |
dp-arm <dimitris.papastamos@arm.com> |
Introduce ARM SiP service
This patch adds ARM SiP service for use by ARM standard platforms. This service is added to support the SMC interface for the Performance measurement framework(PMF).
Chang
Introduce ARM SiP service
This patch adds ARM SiP service for use by ARM standard platforms. This service is added to support the SMC interface for the Performance measurement framework(PMF).
Change-Id: I26f5712f9ab54f5f721dd4781e35a16f40aacc44 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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| d9915518 | 30-Jun-2016 |
Yatharth Kochar <yatharth.kochar@arm.com> |
AArch32: Support in SP_MIN to receive arguments from BL2
This patch adds support in SP_MIN to receive generic and platform specific arguments from BL2.
The new signature is as following: void s
AArch32: Support in SP_MIN to receive arguments from BL2
This patch adds support in SP_MIN to receive generic and platform specific arguments from BL2.
The new signature is as following: void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2);
ARM platforms have been modified to use this support.
Note: Platforms may break if using old signature. Default value for RESET_TO_SP_MIN is changed to 0.
Change-Id: I008d4b09fd3803c7b6231587ebf02a047bdba8d0
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| a8aa7fec | 13-Sep-2016 |
Yatharth Kochar <yatharth.kochar@arm.com> |
ARM platform changes for new version of image loading
This patch adds changes in ARM platform code to use new version of image loading.
Following are the major changes: -Refactor the signatures f
ARM platform changes for new version of image loading
This patch adds changes in ARM platform code to use new version of image loading.
Following are the major changes: -Refactor the signatures for bl31_early_platform_setup() and arm_bl31_early_platform_setup() function to use `void *` instead of `bl31_params_t *`. -Introduce `plat_arm_bl2_handle_scp_bl2()` to handle loading of SCP_BL2 image from BL2. -Remove usage of reserve_mem() function from `arm_bl1_early_platform_setup()` -Extract BL32 & BL33 entrypoint info, from the link list passed by BL2, in `arm_bl31_early_platform_setup()` -Provides weak definitions for following platform functions: plat_get_bl_image_load_info plat_get_next_bl_params plat_flush_next_bl_params bl2_plat_handle_post_image_load -Instantiates a descriptor array for ARM platforms describing image and entrypoint information for `SCP_BL2`, `BL31`, `BL32` and `BL33` images.
All the above changes are conditionally compiled using the `LOAD_IMAGE_V2` flag.
Change-Id: I5e88b9785a3df1a2b2bbbb37d85b8e353ca61049
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| afc931f5 | 15-Sep-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add some missing forward declarations in plat_arm.h
This patch adds a couple of missing forward declarations in plat_arm.h so that all types it references are known within this header file, without
Add some missing forward declarations in plat_arm.h
This patch adds a couple of missing forward declarations in plat_arm.h so that all types it references are known within this header file, without relying on previous header inclusions. This concerns the meminfo and bl31_params structures, which are defined in bl_common.h. Other external types referenced from plat_arm.h (e.g. mmap_region_t) get declared through header files included by arm_plat.h so they don't need forward declarations.
Change-Id: I471d5aa487919aff3fa979fc65e053f4f5b0ef32
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| 181bbd41 | 11-Jul-2016 |
Soby Mathew <soby.mathew@arm.com> |
AArch32: Add FVP support for SP_MIN
This patch implements the support for SP_MIN in FVP. The SP_MIN platform APIs are implemented and the required makefile support is added for FVP.
Change-Id: Id50
AArch32: Add FVP support for SP_MIN
This patch implements the support for SP_MIN in FVP. The SP_MIN platform APIs are implemented and the required makefile support is added for FVP.
Change-Id: Id50bd6093eccbd5e38894e3fd2b20d5baeac5452
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| 877cf3ff | 11-Jul-2016 |
Soby Mathew <soby.mathew@arm.com> |
AArch32: Add essential ARM platform and FVP support
This patch adds AArch32 support for FVP and implements common platform APIs like `plat_get_my_stack`, `plat_set_my_stack`, `plat_my_core_cos` for
AArch32: Add essential ARM platform and FVP support
This patch adds AArch32 support for FVP and implements common platform APIs like `plat_get_my_stack`, `plat_set_my_stack`, `plat_my_core_cos` for AArch32. Only Multi Processor(MP) implementations of these functions are considered in this patch. The ARM Standard platform layer helpers are implemented for AArch32 and the common makefiles are modified to cater for both AArch64 and AArch32 builds. Compatibility with the deprecated platform API is not supported for AArch32.
Change-Id: Iad228400613eec91abf731b49e21a15bcf2833ea
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| 4c0d0390 | 16-Jun-2016 |
Soby Mathew <soby.mathew@arm.com> |
Rework type usage in Trusted Firmware
This patch reworks type usage in generic code, drivers and ARM platform files to make it more portable. The major changes done with respect to type usage are as
Rework type usage in Trusted Firmware
This patch reworks type usage in generic code, drivers and ARM platform files to make it more portable. The major changes done with respect to type usage are as listed below:
* Use uintptr_t for storing address instead of uint64_t or unsigned long. * Review usage of unsigned long as it can no longer be assumed to be 64 bit. * Use u_register_t for register values whose width varies depending on whether AArch64 or AArch32. * Use generic C types where-ever possible.
In addition to the above changes, this patch also modifies format specifiers in print invocations so that they are AArch64/AArch32 agnostic. Only files related to upcoming feature development have been reworked.
Change-Id: I9f8c78347c5a52ba7027ff389791f1dad63ee5f8
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| 0af559a8 | 08-Jul-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
ARM platforms: Add support for SEPARATE_CODE_AND_RODATA
The arm_setup_page_tables() function used to expect a single set of addresses defining the extents of the whole read-only section, code and re
ARM platforms: Add support for SEPARATE_CODE_AND_RODATA
The arm_setup_page_tables() function used to expect a single set of addresses defining the extents of the whole read-only section, code and read-only data mixed up, which was mapped as executable.
This patch changes this behaviour. arm_setup_page_tables() now expects 2 separate sets of addresses:
- the extents of the code section; - the extents of the read-only data section.
The code is mapped as executable, whereas the data is mapped as execute-never. New #defines have been introduced to identify the extents of the code and the read-only data section. Given that all BL images except BL1 share the same memory layout and linker script structure, these #defines are common across these images. The slight memory layout differences in BL1 have been handled by providing values specific to BL1.
Note that this patch also affects the Xilinx platform port, which uses the arm_setup_page_tables() function. It has been updated accordingly, such that the memory mappings on this platform are unchanged. This is achieved by passing null values as the extents of the read-only data section so that it is ignored. As a result, the whole read-only section is still mapped as executable.
Fixes ARM-software/tf-issues#85
Change-Id: I1f95865c53ce6e253a01286ff56e0aa1161abac5
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| ed81f3eb | 05-Jul-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Introduce utils.h header file
This patch introduces a new header file: include/lib/utils.h. Its purpose is to provide generic macros and helper functions that are independent of any BL image, archit
Introduce utils.h header file
This patch introduces a new header file: include/lib/utils.h. Its purpose is to provide generic macros and helper functions that are independent of any BL image, architecture, platform and even not specific to Trusted Firmware.
For now, it contains only 2 macros: ARRAY_SIZE() and IS_POWER_OF_TWO(). These were previously defined in bl_common.h and xlat_tables.c respectively.
bl_common.h includes utils.h to retain compatibility for platforms that relied on bl_common.h for the ARRAY_SIZE() macro. Upstream platform ports that use this macro have been updated to include utils.h.
Change-Id: I960450f54134f25d1710bfbdc4184f12c049a9a9
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| b5fa6563 | 18-May-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Introduce arm_setup_page_tables() function
This patch introduces the arm_setup_page_tables() function to set up page tables on ARM platforms. It replaces the arm_configure_mmu_elx() functions and do
Introduce arm_setup_page_tables() function
This patch introduces the arm_setup_page_tables() function to set up page tables on ARM platforms. It replaces the arm_configure_mmu_elx() functions and does the same thing except that it doesn't enable the MMU at the end. The idea is to reduce the amount of per-EL code that is generated by the C preprocessor by splitting the memory regions definitions and page tables creation (which is generic) from the MMU enablement (which is the only per-EL configuration).
As a consequence, the call to the enable_mmu_elx() function has been moved up into the plat_arch_setup() hook. Any other ARM standard platforms that use the functions `arm_configure_mmu_elx()` must be updated.
Change-Id: I6f12a20ce4e5187b3849a8574aac841a136de83d
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| 9ff67fa6 | 26-Nov-2015 |
Gerald Lejeune <gerald.lejeune@st.com> |
Dump platform-defined regs in crash reporting
It is up to the platform to implement the new plat_crash_print_regs macro to report all relevant platform registers helpful for troubleshooting.
plat_c
Dump platform-defined regs in crash reporting
It is up to the platform to implement the new plat_crash_print_regs macro to report all relevant platform registers helpful for troubleshooting.
plat_crash_print_regs merges or calls previously defined plat_print_gic_regs and plat_print_interconnect_regs macros for each existing platforms.
NOTE: THIS COMMIT REQUIRES ALL PLATFORMS THAT ENABLE THE `CRASH_REPORTING` BUILD FLAG TO MIGRATE TO USE THE NEW `plat_crash_print_regs()` MACRO. BY DEFAULT, `CRASH_REPORTING` IS ENABLED IN DEBUG BUILDS FOR ALL PLATFORMS.
Fixes: arm-software/tf-issues#373
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
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| b2c9687f | 08-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #586 from antonio-nino-diaz-arm/an/spd-bl32
Remove BL32_BASE when building without SPD for FVP |
| 81d139d5 | 05-Apr-2016 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Remove BL32_BASE when building without SPD for FVP
Previously, when building TF without SPD support, BL2 tried to load a BL32 image from the FIP and fails to find one, which resulted on warning mess
Remove BL32_BASE when building without SPD for FVP
Previously, when building TF without SPD support, BL2 tried to load a BL32 image from the FIP and fails to find one, which resulted on warning messages on the console. Even if there is a BL32 image in the FIP it shouldn't be loaded because there is no way to transfer control to the Secure Payload without SPD support.
The Makefile has been modified to pass a define of the form SPD_${SPD} to the source code the same way it's done for PLAT. The define SPD_none is then used to undefine BL32_BASE when BL32 is not used to prevent BL2 from trying to load a BL32 image and failing, thus removing the warning messages mentioned above.
Fixes ARM-software/tf-issues#287
Change-Id: Ifeb6f1c26935efb76afd353fea88e87ba09e9658
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| 105b59e7 | 07-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #575 from soby-mathew/sm/new_tzc_driver
Refactor the TZC driver and add DMC-500 driver |
| 618f0fee | 29-Jan-2016 |
Vikram Kanigiri <vikram.kanigiri@arm.com> |
Add support to program a DMC-500 TZC on ARM platforms
This patch adds support to program TrustZone protection on ARM platforms that implement a DMC-500. arm_dmc_500.c has been added which implements
Add support to program a DMC-500 TZC on ARM platforms
This patch adds support to program TrustZone protection on ARM platforms that implement a DMC-500. arm_dmc_500.c has been added which implements the arm_dmc_tzc_setup() function. This function relies on constants related to TZC programming that are exported by each platform to program TrustZone protection using the DMC-500 TrustZone controller driver. This function should be called from plat_arm_security_setup() which is implemented by each platform.
Change-Id: I5400bdee9e4b29155fd11296a40693d512312f29
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| 57f78201 | 26-Feb-2016 |
Soby Mathew <soby.mathew@arm.com> |
Migrate ARM standard platforms to the refactored TZC driver
This patch migrates ARM Standard platforms to the refactored TZC driver.
Change-Id: I2a2f60b645f73e14d8f416740c4551cec87cb1fb |
| 4518dd9a | 07-Mar-2016 |
David Wang <david.wang@arm.com> |
Add support to load BL31 in DRAM
This patch adds an option to the ARM common platforms to load BL31 in the TZC secured DRAM instead of the default secure SRAM.
To enable this feature, set `ARM_BL31
Add support to load BL31 in DRAM
This patch adds an option to the ARM common platforms to load BL31 in the TZC secured DRAM instead of the default secure SRAM.
To enable this feature, set `ARM_BL31_IN_DRAM` to 1 in build options. If TSP is present, then setting this option also sets the TSP location to DRAM and ignores the `ARM_TSP_RAM_LOCATION` build flag.
To use this feature, BL2 platform code must map in the DRAM used by BL31. The macro ARM_MAP_BL31_SEC_DRAM is provided for this purpose. Currently, only the FVP BL2 platform code maps in this DRAM.
Change-Id: If5f7cc9deb569cfe68353a174d4caa48acd78d67
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| 1a4fdb36 | 26-Feb-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #533 from yatharth-arm/yk/genfw-1292
Fix the inconsistencies in bl1_tbbr_image_descs[] |
| 843ddee4 | 01-Feb-2016 |
Yatharth Kochar <yatharth.kochar@arm.com> |
Fix the inconsistencies in bl1_tbbr_image_descs[]
This patch fixes inconsistencies in bl1_tbbr_image_descs[] and miscellaneous fixes in Firmware Update code.
Following are the changes: * As part of
Fix the inconsistencies in bl1_tbbr_image_descs[]
This patch fixes inconsistencies in bl1_tbbr_image_descs[] and miscellaneous fixes in Firmware Update code.
Following are the changes: * As part of the original FWU changes, a `copied_size` field was added to `image_info_t`. This was a subtle binary compatibility break because it changed the size of the `bl31_params_t` struct, which could cause problems if somebody used different versions of BL2 or BL31, one with the old `image_info_t` and one with the new version. This patch put the `copied_size` within the `image_desc_t`. * EXECUTABLE flag is now stored in `ep_info.h.attr` in place of `image_info.h.attr`, associating it to an entrypoint. * The `image_info.image_base` is only relevant for secure images that are copied from non-secure memory into secure memory. This patch removes initializing `image_base` for non secure images in the bl1_tbbr_image_descs[]. * A new macro `SET_STATIC_PARAM_HEAD` is added for populating bl1_tbbr_image_descs[].ep_info/image_info.h members statically. The version, image_type and image attributes are now populated using this new macro. * Added PLAT_ARM_NVM_BASE and PLAT_ARM_NVM_SIZE to avoid direct usage of V2M_FLASH0_XXX in plat/arm/common/arm_bl1_fwu.c. * Refactoring of code/macros related to SECURE and EXECUTABLE flags.
NOTE: PLATFORM PORTS THAT RELY ON THE SIZE OF `image_info_t` OR USE the "EXECUTABLE" BIT WITHIN `image_info_t.h.attr` OR USE THEIR OWN `image_desc_t` ARRAY IN BL1, MAY BE BROKEN BY THIS CHANGE. THIS IS CONSIDERED UNLIKELY.
Change-Id: Id4e5989af7bf0ed263d19d3751939da1169b561d
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| f62d89ed | 19-Feb-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #531 from soby-mathew/sm/multicluster_fvp
Allow multi cluster topology definitions for ARM platforms |
| 0108047a | 01-Feb-2016 |
Soby Mathew <soby.mathew@arm.com> |
Allow multi cluster topology definitions for ARM platforms
The common topology description helper funtions and macros for ARM Standard platforms assumed a dual cluster system. This is not flexible e
Allow multi cluster topology definitions for ARM platforms
The common topology description helper funtions and macros for ARM Standard platforms assumed a dual cluster system. This is not flexible enough to scale to multi cluster platforms. This patch does the following changes for more flexibility in defining topology:
1. The `plat_get_power_domain_tree_desc()` definition is moved from `arm_topology.c` to platform specific files, that is `fvp_topology.c` and `juno_topology.c`. Similarly the common definition of the porting macro `PLATFORM_CORE_COUNT` in `arm_def.h` is moved to platform specific `platform_def.h` header.
2. The ARM common layer porting macros which were dual cluster specific are now removed and a new macro PLAT_ARM_CLUSTER_COUNT is introduced which must be defined by each ARM standard platform.
3. A new mandatory ARM common layer porting API `plat_arm_get_cluster_core_count()` is introduced to enable the common implementation of `arm_check_mpidr()` to validate MPIDR.
4. For the FVP platforms, a new build option `FVP_NUM_CLUSTERS` has been introduced which allows the user to specify the cluster count to be used to build the topology tree within Trusted Firmare. This enables Trusted Firmware to be built for multi cluster FVP models.
Change-Id: Ie7a2e38e5661fe2fdb2c8fdf5641d2b2614c2b6b
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| 85df7e44 | 18-Feb-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #523 from jcastillo-arm/jc/genfw-791
ARM platforms: rationalise memory attributes of shared memory |
| 74eb26e4 | 13-Jan-2016 |
Juan Castillo <juan.castillo@arm.com> |
ARM platforms: rationalise memory attributes of shared memory
The shared memory region on ARM platforms contains the mailboxes and, on Juno, the payload area for communication with the SCP. This sha
ARM platforms: rationalise memory attributes of shared memory
The shared memory region on ARM platforms contains the mailboxes and, on Juno, the payload area for communication with the SCP. This shared memory may be configured as normal memory or device memory at build time by setting the platform flag 'PLAT_ARM_SHARED_RAM_CACHED' (on Juno, the value of this flag is defined by 'MHU_PAYLOAD_CACHED'). When set as normal memory, the platform port performs the corresponding cache maintenance operations. From a functional point of view, this is the equivalent of setting the shared memory as device memory, so there is no need to maintain both options.
This patch removes the option to specify the shared memory as normal memory on ARM platforms. Shared memory is always treated as device memory. Cache maintenance operations are no longer needed and have been replaced by data memory barriers to guarantee that payload and MHU are accessed in the right order.
Change-Id: I7f958621d6a536dd4f0fa8768385eedc4295e79f
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| 6355f234 | 15-Feb-2016 |
Vikram Kanigiri <vikram.kanigiri@arm.com> |
Rework use of interconnect drivers
ARM Trusted Firmware supports 2 different interconnect peripheral drivers: CCI and CCN. ARM platforms are implemented using either of the interconnect peripherals.
Rework use of interconnect drivers
ARM Trusted Firmware supports 2 different interconnect peripheral drivers: CCI and CCN. ARM platforms are implemented using either of the interconnect peripherals.
This patch adds a layer of abstraction to help ARM platform ports to choose the right interconnect driver and corresponding platform support. This is as described below:
1. A set of ARM common functions have been implemented to initialise an interconnect and for entering/exiting a cluster from coherency. These functions are prefixed as "plat_arm_interconnect_". Weak definitions of these functions have been provided for each type of driver.
2.`plat_print_interconnect_regs` macro used for printing CCI registers is moved from a common arm_macros.S to cci_macros.S.
3. The `ARM_CONFIG_HAS_CCI` flag used in `arm_config_flags` structure is renamed to `ARM_CONFIG_HAS_INTERCONNECT`.
Change-Id: I02f31184fbf79b784175892d5ce1161b65a0066c
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