1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef __ARM_DEF_H__ 31 #define __ARM_DEF_H__ 32 33 #include <arch.h> 34 #include <common_def.h> 35 #include <platform_def.h> 36 #include <tbbr_img_def.h> 37 #include <xlat_tables.h> 38 39 40 /****************************************************************************** 41 * Definitions common to all ARM standard platforms 42 *****************************************************************************/ 43 44 /* Special value used to verify platform parameters from BL2 to BL31 */ 45 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 46 47 #define ARM_CLUSTER_COUNT 2 48 #define ARM_SYSTEM_COUNT 1 49 50 #define ARM_CACHE_WRITEBACK_SHIFT 6 51 52 /* 53 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 54 * power levels have a 1:1 mapping with the MPIDR affinity levels. 55 */ 56 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 57 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 58 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 59 60 /* 61 * Macros for local power states in ARM platforms encoded by State-ID field 62 * within the power-state parameter. 63 */ 64 /* Local power state for power domains in Run state. */ 65 #define ARM_LOCAL_STATE_RUN 0 66 /* Local power state for retention. Valid only for CPU power domains */ 67 #define ARM_LOCAL_STATE_RET 1 68 /* Local power state for OFF/power-down. Valid for CPU and cluster power 69 domains */ 70 #define ARM_LOCAL_STATE_OFF 2 71 72 /* Memory location options for TSP */ 73 #define ARM_TRUSTED_SRAM_ID 0 74 #define ARM_TRUSTED_DRAM_ID 1 75 #define ARM_DRAM_ID 2 76 77 /* The first 4KB of Trusted SRAM are used as shared memory */ 78 #define ARM_TRUSTED_SRAM_BASE 0x04000000 79 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 80 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 81 82 /* The remaining Trusted SRAM is used to load the BL images */ 83 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 84 ARM_SHARED_RAM_SIZE) 85 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 86 ARM_SHARED_RAM_SIZE) 87 88 /* 89 * The top 16MB of DRAM1 is configured as secure access only using the TZC 90 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 91 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 92 */ 93 #define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000) 94 95 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 96 ARM_DRAM1_SIZE - \ 97 ARM_SCP_TZC_DRAM1_SIZE) 98 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 99 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 100 ARM_SCP_TZC_DRAM1_SIZE - 1) 101 102 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 103 ARM_DRAM1_SIZE - \ 104 ARM_TZC_DRAM1_SIZE) 105 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 106 ARM_SCP_TZC_DRAM1_SIZE) 107 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 108 ARM_AP_TZC_DRAM1_SIZE - 1) 109 110 111 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 112 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 113 ARM_TZC_DRAM1_SIZE) 114 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 115 ARM_NS_DRAM1_SIZE - 1) 116 117 #define ARM_DRAM1_BASE MAKE_ULL(0x80000000) 118 #define ARM_DRAM1_SIZE MAKE_ULL(0x80000000) 119 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 120 ARM_DRAM1_SIZE - 1) 121 122 #define ARM_DRAM2_BASE MAKE_ULL(0x880000000) 123 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 124 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 125 ARM_DRAM2_SIZE - 1) 126 127 #define ARM_IRQ_SEC_PHY_TIMER 29 128 129 #define ARM_IRQ_SEC_SGI_0 8 130 #define ARM_IRQ_SEC_SGI_1 9 131 #define ARM_IRQ_SEC_SGI_2 10 132 #define ARM_IRQ_SEC_SGI_3 11 133 #define ARM_IRQ_SEC_SGI_4 12 134 #define ARM_IRQ_SEC_SGI_5 13 135 #define ARM_IRQ_SEC_SGI_6 14 136 #define ARM_IRQ_SEC_SGI_7 15 137 138 /* 139 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 140 * terminology. On a GICv2 system or mode, the lists will be merged and treated 141 * as Group 0 interrupts. 142 */ 143 #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 144 ARM_IRQ_SEC_SGI_1, \ 145 ARM_IRQ_SEC_SGI_2, \ 146 ARM_IRQ_SEC_SGI_3, \ 147 ARM_IRQ_SEC_SGI_4, \ 148 ARM_IRQ_SEC_SGI_5, \ 149 ARM_IRQ_SEC_SGI_7 150 151 #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ 152 ARM_IRQ_SEC_SGI_6 153 154 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 155 ARM_SHARED_RAM_BASE, \ 156 ARM_SHARED_RAM_SIZE, \ 157 MT_DEVICE | MT_RW | MT_SECURE) 158 159 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 160 ARM_NS_DRAM1_BASE, \ 161 ARM_NS_DRAM1_SIZE, \ 162 MT_MEMORY | MT_RW | MT_NS) 163 164 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 165 TSP_SEC_MEM_BASE, \ 166 TSP_SEC_MEM_SIZE, \ 167 MT_MEMORY | MT_RW | MT_SECURE) 168 169 170 /* 171 * The number of regions like RO(code), coherent and data required by 172 * different BL stages which need to be mapped in the MMU. 173 */ 174 #if USE_COHERENT_MEM 175 #define ARM_BL_REGIONS 3 176 #else 177 #define ARM_BL_REGIONS 2 178 #endif 179 180 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 181 ARM_BL_REGIONS) 182 183 /* Memory mapped Generic timer interfaces */ 184 #define ARM_SYS_CNTCTL_BASE 0x2a430000 185 #define ARM_SYS_CNTREAD_BASE 0x2a800000 186 #define ARM_SYS_TIMCTL_BASE 0x2a810000 187 188 #define ARM_CONSOLE_BAUDRATE 115200 189 190 /* Trusted Watchdog constants */ 191 #define ARM_SP805_TWDG_BASE 0x2a490000 192 #define ARM_SP805_TWDG_CLK_HZ 32768 193 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 194 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 195 #define ARM_TWDG_TIMEOUT_SEC 128 196 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 197 ARM_TWDG_TIMEOUT_SEC) 198 199 /****************************************************************************** 200 * Required platform porting definitions common to all ARM standard platforms 201 *****************************************************************************/ 202 203 #define ADDR_SPACE_SIZE (1ull << 32) 204 205 /* 206 * This macro defines the deepest retention state possible. A higher state 207 * id will represent an invalid or a power down state. 208 */ 209 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 210 211 /* 212 * This macro defines the deepest power down states possible. Any state ID 213 * higher than this is invalid. 214 */ 215 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 216 217 218 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER0_CORE_COUNT + \ 219 PLAT_ARM_CLUSTER1_CORE_COUNT) 220 221 /* 222 * Some data must be aligned on the biggest cache line size in the platform. 223 * This is known only to the platform as it might have a combination of 224 * integrated and external caches. 225 */ 226 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 227 228 229 /******************************************************************************* 230 * BL1 specific defines. 231 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 232 * addresses. 233 ******************************************************************************/ 234 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 235 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 236 + PLAT_ARM_TRUSTED_ROM_SIZE) 237 /* 238 * Put BL1 RW at the top of the Trusted SRAM. 239 */ 240 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 241 ARM_BL_RAM_SIZE - \ 242 PLAT_ARM_MAX_BL1_RW_SIZE) 243 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 244 245 /******************************************************************************* 246 * BL2 specific defines. 247 ******************************************************************************/ 248 /* 249 * Put BL2 just below BL31. 250 */ 251 #define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) 252 #define BL2_LIMIT BL31_BASE 253 254 /******************************************************************************* 255 * BL31 specific defines. 256 ******************************************************************************/ 257 /* 258 * Put BL31 at the top of the Trusted SRAM. 259 */ 260 #define BL31_BASE (ARM_BL_RAM_BASE + \ 261 ARM_BL_RAM_SIZE - \ 262 PLAT_ARM_MAX_BL31_SIZE) 263 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 264 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 265 266 /******************************************************************************* 267 * BL32 specific defines. 268 ******************************************************************************/ 269 /* 270 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 271 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 272 * controller. 273 */ 274 #if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 275 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 276 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 277 # define TSP_PROGBITS_LIMIT BL2_BASE 278 # define BL32_BASE ARM_BL_RAM_BASE 279 # define BL32_LIMIT BL31_BASE 280 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 281 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 282 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 283 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 284 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 285 + (1 << 21)) 286 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 287 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 288 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 289 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 290 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 291 ARM_AP_TZC_DRAM1_SIZE) 292 #else 293 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 294 #endif 295 296 /******************************************************************************* 297 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 298 ******************************************************************************/ 299 #define BL2U_BASE BL2_BASE 300 #define BL2U_LIMIT BL31_BASE 301 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 302 #define NS_BL1U_BASE (V2M_FLASH0_BASE + 0x03EB8000) 303 304 /* 305 * ID of the secure physical generic timer interrupt used by the TSP. 306 */ 307 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 308 309 310 /* 311 * One cache line needed for bakery locks on ARM platforms 312 */ 313 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 314 315 316 #endif /* __ARM_DEF_H__ */ 317