1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <cassert.h> 35 #include <platform_def.h> 36 #include <utils.h> 37 #include <xlat_tables.h> 38 #include "../xlat_tables_private.h" 39 40 /* 41 * The virtual address space size must be a power of two (as set in TCR.T0SZ). 42 * As we start the initial lookup at level 1, it must also be between 2 GB and 43 * 512 GB (with the virtual address size therefore 31 to 39 bits). See section 44 * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.i) for more 45 * information. 46 */ 47 CASSERT(ADDR_SPACE_SIZE >= (1ull << 31) && ADDR_SPACE_SIZE <= (1ull << 39) && 48 IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size); 49 50 #define UNSET_DESC ~0ul 51 #define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) 52 53 static uint64_t l1_xlation_table[NUM_L1_ENTRIES] 54 __aligned(NUM_L1_ENTRIES * sizeof(uint64_t)); 55 56 static unsigned long long tcr_ps_bits; 57 58 static unsigned long long calc_physical_addr_size_bits( 59 unsigned long long max_addr) 60 { 61 /* Physical address can't exceed 48 bits */ 62 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 63 64 /* 48 bits address */ 65 if (max_addr & ADDR_MASK_44_TO_47) 66 return TCR_PS_BITS_256TB; 67 68 /* 44 bits address */ 69 if (max_addr & ADDR_MASK_42_TO_43) 70 return TCR_PS_BITS_16TB; 71 72 /* 42 bits address */ 73 if (max_addr & ADDR_MASK_40_TO_41) 74 return TCR_PS_BITS_4TB; 75 76 /* 40 bits address */ 77 if (max_addr & ADDR_MASK_36_TO_39) 78 return TCR_PS_BITS_1TB; 79 80 /* 36 bits address */ 81 if (max_addr & ADDR_MASK_32_TO_35) 82 return TCR_PS_BITS_64GB; 83 84 return TCR_PS_BITS_4GB; 85 } 86 87 void init_xlat_tables(void) 88 { 89 unsigned long long max_pa; 90 uintptr_t max_va; 91 print_mmap(); 92 init_xlation_table(0, l1_xlation_table, 1, &max_va, &max_pa); 93 tcr_ps_bits = calc_physical_addr_size_bits(max_pa); 94 assert(max_va < ADDR_SPACE_SIZE); 95 } 96 97 /******************************************************************************* 98 * Macro generating the code for the function enabling the MMU in the given 99 * exception level, assuming that the pagetables have already been created. 100 * 101 * _el: Exception level at which the function will run 102 * _tcr_extra: Extra bits to set in the TCR register. This mask will 103 * be OR'ed with the default TCR value. 104 * _tlbi_fct: Function to invalidate the TLBs at the current 105 * exception level 106 ******************************************************************************/ 107 #define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \ 108 void enable_mmu_el##_el(unsigned int flags) \ 109 { \ 110 uint64_t mair, tcr, ttbr; \ 111 uint32_t sctlr; \ 112 \ 113 assert(IS_IN_EL(_el)); \ 114 assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \ 115 \ 116 /* Set attributes in the right indices of the MAIR */ \ 117 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \ 118 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \ 119 ATTR_IWBWA_OWBWA_NTR_INDEX); \ 120 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \ 121 ATTR_NON_CACHEABLE_INDEX); \ 122 write_mair_el##_el(mair); \ 123 \ 124 /* Invalidate TLBs at the current exception level */ \ 125 _tlbi_fct(); \ 126 \ 127 /* Set TCR bits as well. */ \ 128 /* Inner & outer WBWA & shareable + T0SZ = 32 */ \ 129 tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \ 130 TCR_RGN_INNER_WBA | \ 131 (64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \ 132 tcr |= _tcr_extra; \ 133 write_tcr_el##_el(tcr); \ 134 \ 135 /* Set TTBR bits as well */ \ 136 ttbr = (uint64_t) l1_xlation_table; \ 137 write_ttbr0_el##_el(ttbr); \ 138 \ 139 /* Ensure all translation table writes have drained */ \ 140 /* into memory, the TLB invalidation is complete, */ \ 141 /* and translation register writes are committed */ \ 142 /* before enabling the MMU */ \ 143 dsb(); \ 144 isb(); \ 145 \ 146 sctlr = read_sctlr_el##_el(); \ 147 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ 148 \ 149 if (flags & DISABLE_DCACHE) \ 150 sctlr &= ~SCTLR_C_BIT; \ 151 else \ 152 sctlr |= SCTLR_C_BIT; \ 153 \ 154 write_sctlr_el##_el(sctlr); \ 155 \ 156 /* Ensure the MMU enable takes effect immediately */ \ 157 isb(); \ 158 } 159 160 /* Define EL1 and EL3 variants of the function enabling the MMU */ 161 DEFINE_ENABLE_MMU_EL(1, 162 (tcr_ps_bits << TCR_EL1_IPS_SHIFT), 163 tlbivmalle1) 164 DEFINE_ENABLE_MMU_EL(3, 165 TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT), 166 tlbialle3) 167