1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arm_def.h> 35 #include <board_arm_def.h> 36 #include <board_css_def.h> 37 #include <common_def.h> 38 #include <css_def.h> 39 #include <soc_css_def.h> 40 #include <tzc400.h> 41 #include <v2m_def.h> 42 #include "../juno_def.h" 43 44 /* Required platform porting definitions */ 45 /* Juno supports system power domain */ 46 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 47 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 48 JUNO_CLUSTER_COUNT + \ 49 PLATFORM_CORE_COUNT) 50 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 51 JUNO_CLUSTER1_CORE_COUNT) 52 53 /* 54 * Other platform porting definitions are provided by included headers 55 */ 56 57 /* 58 * Required ARM standard platform porting definitions 59 */ 60 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 61 62 /* Use the bypass address */ 63 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 64 65 /* 66 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 67 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 68 * flash 69 */ 70 #if TRUSTED_BOARD_BOOT 71 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 72 #else 73 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 74 #endif /* TRUSTED_BOARD_BOOT */ 75 76 77 /* CCI related constants */ 78 #define PLAT_ARM_CCI_BASE 0x2c090000 79 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 80 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 81 82 /* System timer related constants */ 83 #define PLAT_ARM_NSTIMER_FRAME_ID 1 84 85 /* TZC related constants */ 86 #define PLAT_ARM_TZC_BASE 0x2a4a0000 87 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 88 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 89 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 90 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 91 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 92 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 93 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 94 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 95 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 96 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 97 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 98 99 /* 100 * Required ARM CSS based platform porting definitions 101 */ 102 103 /* GIC related constants (no GICR in GIC-400) */ 104 #define PLAT_ARM_GICD_BASE 0x2c010000 105 #define PLAT_ARM_GICC_BASE 0x2c02f000 106 #define PLAT_ARM_GICH_BASE 0x2c04f000 107 #define PLAT_ARM_GICV_BASE 0x2c06f000 108 109 /* MHU related constants */ 110 #define PLAT_CSS_MHU_BASE 0x2b1f0000 111 112 /* 113 * Base address of the first memory region used for communication between AP 114 * and SCP. Used by the BOM and SCPI protocols. 115 * 116 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 117 * means the SCP/AP configuration data gets overwritten when the AP initiates 118 * communication with the SCP. The configuration data is expected to be a 119 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 120 * which CPU is the primary, according to the shift and mask definitions below. 121 */ 122 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 123 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 124 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 125 126 /* 127 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 128 * terminology. On a GICv2 system or mode, the lists will be merged and treated 129 * as Group 0 interrupts. 130 */ 131 #define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ 132 ARM_G1S_IRQS, \ 133 JUNO_IRQ_DMA_SMMU, \ 134 JUNO_IRQ_HDLCD0_SMMU, \ 135 JUNO_IRQ_HDLCD1_SMMU, \ 136 JUNO_IRQ_USB_SMMU, \ 137 JUNO_IRQ_THIN_LINKS_SMMU, \ 138 JUNO_IRQ_SEC_I2C, \ 139 JUNO_IRQ_GPU_SMMU_1, \ 140 JUNO_IRQ_ETR_SMMU 141 142 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 143 144 /* 145 * Required ARM CSS SoC based platform porting definitions 146 */ 147 148 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 149 #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 150 151 /* 152 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 153 * plus a little space for growth. 154 */ 155 #if TRUSTED_BOARD_BOOT 156 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 157 #else 158 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 159 #endif 160 161 /* 162 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 163 * little space for growth. 164 */ 165 #if TRUSTED_BOARD_BOOT 166 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 167 #else 168 # define PLAT_ARM_MAX_BL2_SIZE 0xC000 169 #endif 170 171 /* 172 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 173 * little space for growth. 174 */ 175 #define PLAT_ARM_MAX_BL31_SIZE 0x1D000 176 177 #endif /* __PLATFORM_DEF_H__ */ 178