1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm_config.h> 32 #include <arm_def.h> 33 #include <debug.h> 34 #include <gicv2.h> 35 #include <mmio.h> 36 #include <plat_arm.h> 37 #include <v2m_def.h> 38 #include "../fvp_def.h" 39 40 #if (FVP_USE_GIC_DRIVER == FVP_GICV2) 41 extern gicv2_driver_data_t arm_gic_data; 42 #endif 43 44 /* Defines for GIC Driver build time selection */ 45 #define FVP_GICV2 1 46 #define FVP_GICV3 2 47 #define FVP_GICV3_LEGACY 3 48 49 /******************************************************************************* 50 * arm_config holds the characteristics of the differences between the three FVP 51 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 52 * at each boot stage by the primary before enabling the MMU (to allow 53 * interconnect configuration) & used thereafter. Each BL will have its own copy 54 * to allow independent operation. 55 ******************************************************************************/ 56 arm_config_t arm_config; 57 58 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 59 DEVICE0_SIZE, \ 60 MT_DEVICE | MT_RW | MT_SECURE) 61 62 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 63 DEVICE1_SIZE, \ 64 MT_DEVICE | MT_RW | MT_SECURE) 65 66 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 67 DEVICE2_SIZE, \ 68 MT_DEVICE | MT_RO | MT_SECURE) 69 70 71 /* 72 * Table of regions for various BL stages to map using the MMU. 73 * This doesn't include TZRAM as the 'mem_layout' argument passed to 74 * arm_configure_mmu_elx() will give the available subset of that, 75 */ 76 #if IMAGE_BL1 77 const mmap_region_t plat_arm_mmap[] = { 78 ARM_MAP_SHARED_RAM, 79 V2M_MAP_FLASH0_RW, 80 V2M_MAP_IOFPGA, 81 MAP_DEVICE0, 82 MAP_DEVICE1, 83 MAP_DEVICE2, 84 #if TRUSTED_BOARD_BOOT 85 ARM_MAP_NS_DRAM1, 86 #endif 87 {0} 88 }; 89 #endif 90 #if IMAGE_BL2 91 const mmap_region_t plat_arm_mmap[] = { 92 ARM_MAP_SHARED_RAM, 93 V2M_MAP_FLASH0_RW, 94 V2M_MAP_IOFPGA, 95 MAP_DEVICE0, 96 MAP_DEVICE1, 97 MAP_DEVICE2, 98 ARM_MAP_NS_DRAM1, 99 ARM_MAP_TSP_SEC_MEM, 100 #if ARM_BL31_IN_DRAM 101 ARM_MAP_BL31_SEC_DRAM, 102 #endif 103 {0} 104 }; 105 #endif 106 #if IMAGE_BL2U 107 const mmap_region_t plat_arm_mmap[] = { 108 MAP_DEVICE0, 109 V2M_MAP_IOFPGA, 110 {0} 111 }; 112 #endif 113 #if IMAGE_BL31 114 const mmap_region_t plat_arm_mmap[] = { 115 ARM_MAP_SHARED_RAM, 116 V2M_MAP_IOFPGA, 117 MAP_DEVICE0, 118 MAP_DEVICE1, 119 {0} 120 }; 121 #endif 122 #if IMAGE_BL32 123 const mmap_region_t plat_arm_mmap[] = { 124 V2M_MAP_IOFPGA, 125 MAP_DEVICE0, 126 MAP_DEVICE1, 127 {0} 128 }; 129 #endif 130 131 ARM_CASSERT_MMAP 132 133 134 /******************************************************************************* 135 * A single boot loader stack is expected to work on both the Foundation FVP 136 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 137 * SYS_ID register provides a mechanism for detecting the differences between 138 * these platforms. This information is stored in a per-BL array to allow the 139 * code to take the correct path.Per BL platform configuration. 140 ******************************************************************************/ 141 void fvp_config_setup(void) 142 { 143 unsigned int rev, hbi, bld, arch, sys_id; 144 145 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 146 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 147 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 148 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 149 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 150 151 if (arch != ARCH_MODEL) { 152 ERROR("This firmware is for FVP models\n"); 153 panic(); 154 } 155 156 /* 157 * The build field in the SYS_ID tells which variant of the GIC 158 * memory is implemented by the model. 159 */ 160 switch (bld) { 161 case BLD_GIC_VE_MMAP: 162 #if IMAGE_BL31 || IMAGE_BL32 163 #if FVP_USE_GIC_DRIVER == FVP_GICV2 164 /* 165 * If the FVP implements the VE compatible memory map, then the 166 * GICv2 driver must be included in the build. Update the platform 167 * data with the correct GICv2 base addresses before it is used 168 * to initialise the driver. 169 * 170 * This update of platform data is temporary and will be removed 171 * once VE memory map for FVP is no longer supported by Trusted 172 * Firmware. 173 */ 174 arm_gic_data.gicd_base = VE_GICD_BASE; 175 arm_gic_data.gicc_base = VE_GICC_BASE; 176 177 #else 178 ERROR("Only GICv2 driver supported for VE memory map\n"); 179 panic(); 180 #endif /* __FVP_USE_GIC_DRIVER == FVP_GICV2__ */ 181 #endif /* __IMAGE_BL31 || IMAGE_BL32__ */ 182 break; 183 case BLD_GIC_A53A57_MMAP: 184 break; 185 default: 186 ERROR("Unsupported board build %x\n", bld); 187 panic(); 188 } 189 190 /* 191 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 192 * for the Foundation FVP. 193 */ 194 switch (hbi) { 195 case HBI_FOUNDATION_FVP: 196 arm_config.flags = 0; 197 198 /* 199 * Check for supported revisions of Foundation FVP 200 * Allow future revisions to run but emit warning diagnostic 201 */ 202 switch (rev) { 203 case REV_FOUNDATION_FVP_V2_0: 204 case REV_FOUNDATION_FVP_V2_1: 205 case REV_FOUNDATION_FVP_v9_1: 206 break; 207 default: 208 WARN("Unrecognized Foundation FVP revision %x\n", rev); 209 break; 210 } 211 break; 212 case HBI_BASE_FVP: 213 arm_config.flags |= ARM_CONFIG_BASE_MMAP | 214 ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC; 215 216 /* 217 * Check for supported revisions 218 * Allow future revisions to run but emit warning diagnostic 219 */ 220 switch (rev) { 221 case REV_BASE_FVP_V0: 222 break; 223 default: 224 WARN("Unrecognized Base FVP revision %x\n", rev); 225 break; 226 } 227 break; 228 default: 229 ERROR("Unsupported board HBI number 0x%x\n", hbi); 230 panic(); 231 } 232 } 233 234 235 void fvp_interconnect_init(void) 236 { 237 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 238 plat_arm_interconnect_init(); 239 } 240 241 void fvp_interconnect_enable(void) 242 { 243 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 244 plat_arm_interconnect_enter_coherency(); 245 } 246 247 void fvp_interconnect_disable(void) 248 { 249 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 250 plat_arm_interconnect_exit_coherency(); 251 } 252