1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <arm_def.h> 34 #include <assert.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <mmio.h> 38 #include <plat_arm.h> 39 #include <platform.h> 40 41 42 /* 43 * The next 3 constants identify the extents of the code, RO data region and the 44 * limit of the BL31 image. These addresses are used by the MMU setup code and 45 * therefore they must be page-aligned. It is the responsibility of the linker 46 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 47 * refer to page-aligned addresses. 48 */ 49 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 50 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 51 #define BL31_END (unsigned long)(&__BL31_END__) 52 53 #if USE_COHERENT_MEM 54 /* 55 * The next 2 constants identify the extents of the coherent memory region. 56 * These addresses are used by the MMU setup code and therefore they must be 57 * page-aligned. It is the responsibility of the linker script to ensure that 58 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 59 * refer to page-aligned addresses. 60 */ 61 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 62 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 63 #endif 64 65 /* 66 * Placeholder variables for copying the arguments that have been passed to 67 * BL31 from BL2. 68 */ 69 static entry_point_info_t bl32_image_ep_info; 70 static entry_point_info_t bl33_image_ep_info; 71 72 73 /* Weak definitions may be overridden in specific ARM standard platform */ 74 #pragma weak bl31_early_platform_setup 75 #pragma weak bl31_platform_setup 76 #pragma weak bl31_plat_arch_setup 77 #pragma weak bl31_plat_get_next_image_ep_info 78 79 80 /******************************************************************************* 81 * Return a pointer to the 'entry_point_info' structure of the next image for the 82 * security state specified. BL33 corresponds to the non-secure image type 83 * while BL32 corresponds to the secure image type. A NULL pointer is returned 84 * if the image does not exist. 85 ******************************************************************************/ 86 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 87 { 88 entry_point_info_t *next_image_info; 89 90 assert(sec_state_is_valid(type)); 91 next_image_info = (type == NON_SECURE) 92 ? &bl33_image_ep_info : &bl32_image_ep_info; 93 /* 94 * None of the images on the ARM development platforms can have 0x0 95 * as the entrypoint 96 */ 97 if (next_image_info->pc) 98 return next_image_info; 99 else 100 return NULL; 101 } 102 103 /******************************************************************************* 104 * Perform any BL31 early platform setup common to ARM standard platforms. 105 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 106 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 107 * done before the MMU is initialized so that the memory layout can be used 108 * while creating page tables. BL2 has flushed this information to memory, so 109 * we are guaranteed to pick up good data. 110 ******************************************************************************/ 111 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, 112 void *plat_params_from_bl2) 113 { 114 /* Initialize the console to provide early debug support */ 115 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 116 ARM_CONSOLE_BAUDRATE); 117 118 #if RESET_TO_BL31 119 /* There are no parameters from BL2 if BL31 is a reset vector */ 120 assert(from_bl2 == NULL); 121 assert(plat_params_from_bl2 == NULL); 122 123 #ifdef BL32_BASE 124 /* Populate entry point information for BL32 */ 125 SET_PARAM_HEAD(&bl32_image_ep_info, 126 PARAM_EP, 127 VERSION_1, 128 0); 129 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 130 bl32_image_ep_info.pc = BL32_BASE; 131 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 132 #endif /* BL32_BASE */ 133 134 /* Populate entry point information for BL33 */ 135 SET_PARAM_HEAD(&bl33_image_ep_info, 136 PARAM_EP, 137 VERSION_1, 138 0); 139 /* 140 * Tell BL31 where the non-trusted software image 141 * is located and the entry state information 142 */ 143 #ifdef PRELOADED_BL33_BASE 144 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 145 #else 146 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 147 #endif /* PRELOADED_BL33_BASE */ 148 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 149 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 150 151 #else 152 /* 153 * Check params passed from BL2 should not be NULL, 154 */ 155 assert(from_bl2 != NULL); 156 assert(from_bl2->h.type == PARAM_BL31); 157 assert(from_bl2->h.version >= VERSION_1); 158 /* 159 * In debug builds, we pass a special value in 'plat_params_from_bl2' 160 * to verify platform parameters from BL2 to BL31. 161 * In release builds, it's not used. 162 */ 163 assert(((unsigned long long)plat_params_from_bl2) == 164 ARM_BL31_PLAT_PARAM_VAL); 165 166 /* 167 * Copy BL32 (if populated by BL2) and BL33 entry point information. 168 * They are stored in Secure RAM, in BL2's address space. 169 */ 170 if (from_bl2->bl32_ep_info) 171 bl32_image_ep_info = *from_bl2->bl32_ep_info; 172 bl33_image_ep_info = *from_bl2->bl33_ep_info; 173 #endif 174 } 175 176 void bl31_early_platform_setup(bl31_params_t *from_bl2, 177 void *plat_params_from_bl2) 178 { 179 arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); 180 181 /* 182 * Initialize Interconnect for this cluster during cold boot. 183 * No need for locks as no other CPU is active. 184 */ 185 plat_arm_interconnect_init(); 186 187 /* 188 * Enable Interconnect coherency for the primary CPU's cluster. 189 * Earlier bootloader stages might already do this (e.g. Trusted 190 * Firmware's BL1 does it) but we can't assume so. There is no harm in 191 * executing this code twice anyway. 192 * Platform specific PSCI code will enable coherency for other 193 * clusters. 194 */ 195 plat_arm_interconnect_enter_coherency(); 196 } 197 198 /******************************************************************************* 199 * Perform any BL31 platform setup common to ARM standard platforms 200 ******************************************************************************/ 201 void arm_bl31_platform_setup(void) 202 { 203 /* Initialize the GIC driver, cpu and distributor interfaces */ 204 plat_arm_gic_driver_init(); 205 plat_arm_gic_init(); 206 207 #if RESET_TO_BL31 208 /* 209 * Do initial security configuration to allow DRAM/device access 210 * (if earlier BL has not already done so). 211 */ 212 plat_arm_security_setup(); 213 214 #endif /* RESET_TO_BL31 */ 215 216 /* Enable and initialize the System level generic timer */ 217 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 218 CNTCR_FCREQ(0) | CNTCR_EN); 219 220 /* Allow access to the System counter timer module */ 221 arm_configure_sys_timer(); 222 223 /* Initialize power controller before setting up topology */ 224 plat_arm_pwrc_setup(); 225 } 226 227 /******************************************************************************* 228 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 229 * standard platforms 230 ******************************************************************************/ 231 void arm_bl31_plat_runtime_setup(void) 232 { 233 /* Initialize the runtime console */ 234 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, 235 ARM_CONSOLE_BAUDRATE); 236 } 237 238 void bl31_platform_setup(void) 239 { 240 arm_bl31_platform_setup(); 241 } 242 243 void bl31_plat_runtime_setup(void) 244 { 245 arm_bl31_plat_runtime_setup(); 246 } 247 248 /******************************************************************************* 249 * Perform the very early platform specific architectural setup shared between 250 * ARM standard platforms. This only does basic initialization. Later 251 * architectural setup (bl31_arch_setup()) does not do anything platform 252 * specific. 253 ******************************************************************************/ 254 void arm_bl31_plat_arch_setup(void) 255 { 256 arm_setup_page_tables(BL31_RO_BASE, 257 (BL31_END - BL31_RO_BASE), 258 BL31_RO_BASE, 259 BL31_RO_LIMIT 260 #if USE_COHERENT_MEM 261 , BL31_COHERENT_RAM_BASE, 262 BL31_COHERENT_RAM_LIMIT 263 #endif 264 ); 265 enable_mmu_el3(0); 266 } 267 268 void bl31_plat_arch_setup(void) 269 { 270 arm_bl31_plat_arch_setup(); 271 } 272