1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arm_def.h> 33 #include <bl_common.h> 34 #include <console.h> 35 #include <platform_def.h> 36 #include <plat_arm.h> 37 #include <sp805.h> 38 #include "../../../bl1/bl1_private.h" 39 40 41 #if USE_COHERENT_MEM 42 /* 43 * The next 2 constants identify the extents of the coherent memory region. 44 * These addresses are used by the MMU setup code and therefore they must be 45 * page-aligned. It is the responsibility of the linker script to ensure that 46 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 47 * page-aligned addresses. 48 */ 49 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 50 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 51 #endif 52 53 54 /* Weak definitions may be overridden in specific ARM standard platform */ 55 #pragma weak bl1_early_platform_setup 56 #pragma weak bl1_plat_arch_setup 57 #pragma weak bl1_platform_setup 58 #pragma weak bl1_plat_sec_mem_layout 59 60 61 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 62 static meminfo_t bl1_tzram_layout; 63 64 meminfo_t *bl1_plat_sec_mem_layout(void) 65 { 66 return &bl1_tzram_layout; 67 } 68 69 /******************************************************************************* 70 * BL1 specific platform actions shared between ARM standard platforms. 71 ******************************************************************************/ 72 void arm_bl1_early_platform_setup(void) 73 { 74 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; 75 76 #if !ARM_DISABLE_TRUSTED_WDOG 77 /* Enable watchdog */ 78 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 79 #endif 80 81 /* Initialize the console to provide early debug support */ 82 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 83 ARM_CONSOLE_BAUDRATE); 84 85 /* Allow BL1 to see the whole Trusted RAM */ 86 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 87 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 88 89 /* Calculate how much RAM BL1 is using and how much remains free */ 90 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; 91 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; 92 reserve_mem(&bl1_tzram_layout.free_base, 93 &bl1_tzram_layout.free_size, 94 BL1_RAM_BASE, 95 bl1_size); 96 } 97 98 void bl1_early_platform_setup(void) 99 { 100 arm_bl1_early_platform_setup(); 101 102 /* 103 * Initialize Interconnect for this cluster during cold boot. 104 * No need for locks as no other CPU is active. 105 */ 106 plat_arm_interconnect_init(); 107 /* 108 * Enable Interconnect coherency for the primary CPU's cluster. 109 */ 110 plat_arm_interconnect_enter_coherency(); 111 } 112 113 /****************************************************************************** 114 * Perform the very early platform specific architecture setup shared between 115 * ARM standard platforms. This only does basic initialization. Later 116 * architectural setup (bl1_arch_setup()) does not do anything platform 117 * specific. 118 *****************************************************************************/ 119 void arm_bl1_plat_arch_setup(void) 120 { 121 arm_setup_page_tables(bl1_tzram_layout.total_base, 122 bl1_tzram_layout.total_size, 123 BL1_RO_BASE, 124 BL1_RO_LIMIT 125 #if USE_COHERENT_MEM 126 , BL1_COHERENT_RAM_BASE, 127 BL1_COHERENT_RAM_LIMIT 128 #endif 129 ); 130 enable_mmu_el3(0); 131 } 132 133 void bl1_plat_arch_setup(void) 134 { 135 arm_bl1_plat_arch_setup(); 136 } 137 138 /* 139 * Perform the platform specific architecture setup shared between 140 * ARM standard platforms. 141 */ 142 void arm_bl1_platform_setup(void) 143 { 144 /* Initialise the IO layer and register platform IO devices */ 145 plat_arm_io_setup(); 146 } 147 148 void bl1_platform_setup(void) 149 { 150 arm_bl1_platform_setup(); 151 } 152 153 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 154 { 155 #if !ARM_DISABLE_TRUSTED_WDOG 156 /* Disable watchdog before leaving BL1 */ 157 sp805_stop(ARM_SP805_TWDG_BASE); 158 #endif 159 160 #ifdef EL3_PAYLOAD_BASE 161 /* 162 * Program the EL3 payload's entry point address into the CPUs mailbox 163 * in order to release secondary CPUs from their holding pen and make 164 * them jump there. 165 */ 166 arm_program_trusted_mailbox(ep_info->pc); 167 dsbsy(); 168 sev(); 169 #endif 170 } 171