| af1fa796 | 29-Aug-2025 |
John Powell <john.powell@arm.com> |
fix(cpus): workaround for Cortex-A510 erratum 3672349
Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.
fix(cpus): workaround for Cortex-A510 erratum 3672349
Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.
The workaround is to clear the WFE_RET_CTRL and WFI_RET_CTRL fields
in CPUPWRCTLR_EL1 to disable full retention.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/
Change-Id: I9786ab8843a2eab45e650c6af50b6933481527ec
Signed-off-by: John Powell <john.powell@arm.com>
show more ...
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| 4fb7090e | 29-Aug-2025 |
John Powell <john.powell@arm.com> |
fix(cpus): workaround for Cortex-A510 erratum 2420992
Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.
The workaround is to set bit
fix(cpus): workaround for Cortex-A510 erratum 2420992
Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.
The workaround is to set bit 3 in CPUACTLR3_EL1 which will have no
performance impact, but will increase power consumption by 0.3-0.5%.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/
Change-Id: Ia76ba2431d76f14c08b95a998806986190d682c3
Signed-off-by: John Powell <john.powell@arm.com>
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| 63900851 | 11-Sep-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
We've charged the PSCI entrypoint with doing BL31 specific things like
setting up the EL3 context and doing feature detection.
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
We've charged the PSCI entrypoint with doing BL31 specific things like
setting up the EL3 context and doing feature detection. Well, this is
irrelevant for sp_min and not really appropriate for PSCI. So move it to
the bl31_warmboot() function to reflect this correctly and bring the
feature detection a bit earlier, hopefully spotting more errors.
This allows for a pair of minor cleanups - we can pass the core_pos to
psci_warmboot_entrypoint() without having to refetch it, and we can put
the pauth enablement in cm_manage_extensions_el3() along with all
others. The call of that function is kept after the MMU is turned on so
that we have nicer (coherent) access to cpu_data.
Change-Id: Id031cfa0e1d8fe98919a14f9db73eb5bc9e00f67
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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| 759ed946 | 13-Aug-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(cpus): inform the compiler that struct cpu_ops is aligned
The only way to access a cpu_ops structure is through a pointer returned
from assembly so the compiler can't know its alignment and it m
fix(cpus): inform the compiler that struct cpu_ops is aligned
The only way to access a cpu_ops structure is through a pointer returned
from assembly so the compiler can't know its alignment and it must
assume the worst. As a result, it's scared to do 64 bit loads and must
do 8 single byte loads that it then can combine together.
Well, the cpu assembly macros take care to align the cpu_ops entries to
a word boundary so we can propagate that information to the structure
definition as well and removed the compiler's paranoia.
Change-Id: Id38d6f1b92527b8a414cfbb856a5a82c76a1b1a8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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