1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_a710_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_a710 33 34workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946 35 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(15) 36workaround_reset_end cortex_a710, ERRATUM(1901946) 37 38check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 39 40workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 41 ldr x0,=0x6 42 msr S3_6_c15_c8_0,x0 43 ldr x0,=0xF3A08002 44 msr S3_6_c15_c8_2,x0 45 ldr x0,=0xFFF0F7FE 46 msr S3_6_c15_c8_3,x0 47 ldr x0,=0x40000001003ff 48 msr S3_6_c15_c8_1,x0 49 ldr x0,=0x7 50 msr S3_6_c15_c8_0,x0 51 ldr x0,=0xBF200000 52 msr S3_6_c15_c8_2,x0 53 ldr x0,=0xFFEF0000 54 msr S3_6_c15_c8_3,x0 55 ldr x0,=0x40000001003f3 56 msr S3_6_c15_c8_1,x0 57workaround_reset_end cortex_a710, ERRATUM(1987031) 58 59check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 60 61workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 62 /* Stash ERRSELR_EL1 in x2 */ 63 mrs x2, ERRSELR_EL1 64 65 /* Select error record 0 and clear ED bit */ 66 msr ERRSELR_EL1, xzr 67 mrs x1, ERXCTLR_EL1 68 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 69 msr ERXCTLR_EL1, x1 70 71 /* Select error record 1 and clear ED bit */ 72 mov x0, #1 73 msr ERRSELR_EL1, x0 74 mrs x1, ERXCTLR_EL1 75 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 76 msr ERXCTLR_EL1, x1 77 78 /* Restore ERRSELR_EL1 from x2 */ 79 msr ERRSELR_EL1, x2 80workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 81 82check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 83 84workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 85 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 86workaround_reset_end cortex_a710, ERRATUM(2017096) 87 88check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 89 90workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 91 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 92workaround_reset_end cortex_a710, ERRATUM(2055002) 93 94check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 95 96workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 97 ldr x0,=0x3 98 msr S3_6_c15_c8_0,x0 99 ldr x0,=0xF3A08002 100 msr S3_6_c15_c8_2,x0 101 ldr x0,=0xFFF0F7FE 102 msr S3_6_c15_c8_3,x0 103 ldr x0,=0x10002001003FF 104 msr S3_6_c15_c8_1,x0 105 ldr x0,=0x4 106 msr S3_6_c15_c8_0,x0 107 ldr x0,=0xBF200000 108 msr S3_6_c15_c8_2,x0 109 ldr x0,=0xFFEF0000 110 msr S3_6_c15_c8_3,x0 111 ldr x0,=0x10002001003F3 112 msr S3_6_c15_c8_1,x0 113workaround_reset_end cortex_a710, ERRATUM(2081180) 114 115check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 116 117workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 118 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 119workaround_reset_end cortex_a710, ERRATUM(2083908) 120 121check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 122 123workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 124 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 125workaround_reset_end cortex_a710, ERRATUM(2136059) 126 127check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 128 129workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 130 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 131workaround_reset_end cortex_a710, ERRATUM(2147715) 132 133check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 134 135workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 136 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 137 138 ldr x0,=0x5 139 msr CORTEX_A710_CPUPSELR_EL3, x0 140 ldr x0,=0x10F600E000 141 msr CORTEX_A710_CPUPOR_EL3, x0 142 ldr x0,=0x10FF80E000 143 msr CORTEX_A710_CPUPMR_EL3, x0 144 ldr x0,=0x80000000003FF 145 msr CORTEX_A710_CPUPCR_EL3, x0 146workaround_reset_end cortex_a710, ERRATUM(2216384) 147 148check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 149 150workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 151 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 152workaround_reset_end cortex_a710, ERRATUM(2267065) 153 154check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 155 156workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 157 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 158workaround_reset_end cortex_a710, ERRATUM(2282622) 159 160check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 161 162.global erratum_cortex_a710_2291219_wa 163workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 164 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 165 * the workaround. Second call clears it to undo it. */ 166 sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 167workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 168 169check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 170 171workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941 172 errata_dsu_2313941_wa_impl 173workaround_reset_end cortex_a710, ERRATUM(2313941) 174 175check_erratum_custom_start cortex_a710, ERRATUM(2313941) 176 check_errata_dsu_2313941_impl 177 ret 178check_erratum_custom_end cortex_a710, ERRATUM(2313941) 179 180workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 181 /* Set bit 40 in CPUACTLR2_EL1 */ 182 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 183workaround_reset_end cortex_a710, ERRATUM(2371105) 184 185check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 186 187workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 188 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 189 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 190 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 191workaround_reset_end cortex_a710, ERRATUM(2742423) 192 193check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 194 195workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 196 /* dsb before isb of power down sequence */ 197 dsb sy 198workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 199 200check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 201 202workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 203 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 204workaround_reset_end cortex_a710, ERRATUM(2778471) 205 206check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 207 208add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 209 210check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) 211 212workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 213#if IMAGE_BL31 214 /* 215 * The Cortex-A710 generic vectors are overridden to apply errata 216 * mitigation on exception entry from lower ELs. 217 */ 218 override_vector_table wa_cve_vbar_cortex_a710 219#endif /* IMAGE_BL31 */ 220workaround_reset_end cortex_a710, CVE(2022, 23960) 221 222check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 223 224/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 225workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 226 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 227workaround_reset_end cortex_a710, CVE(2024, 5660) 228 229check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 230 231 /* ---------------------------------------------------- 232 * HW will do the cache maintenance while powering down 233 * ---------------------------------------------------- 234 */ 235func cortex_a710_core_pwr_dwn 236 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV 237 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 238 239 /* --------------------------------------------------- 240 * Enable CPU power down bit in power control register 241 * --------------------------------------------------- 242 */ 243 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 244 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 245 isb 246 ret 247endfunc cortex_a710_core_pwr_dwn 248 249cpu_reset_func_start cortex_a710 250 /* Disable speculative loads */ 251 msr SSBS, xzr 252 enable_mpmm 253cpu_reset_func_end cortex_a710 254 255 /* --------------------------------------------- 256 * This function provides Cortex-A710 specific 257 * register information for crash reporting. 258 * It needs to return with x6 pointing to 259 * a list of register names in ascii and 260 * x8 - x15 having values of registers to be 261 * reported. 262 * --------------------------------------------- 263 */ 264.section .rodata.cortex_a710_regs, "aS" 265cortex_a710_regs: /* The ascii list of register names to be reported */ 266 .asciz "cpuectlr_el1", "" 267 268func cortex_a710_cpu_reg_dump 269 adr x6, cortex_a710_regs 270 mrs x8, CORTEX_A710_CPUECTLR_EL1 271 ret 272endfunc cortex_a710_cpu_reg_dump 273 274declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 275 cortex_a710_reset_func, \ 276 cortex_a710_core_pwr_dwn 277