| 0b77197b | 14-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for Cortex-A57 erratum 829520 workaround
Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439 |
| a8b1c769 | 14-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for Cortex-A57 erratum 828024 workaround
Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d |
| df22d602 | 14-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for Cortex-A57 erratum 826974 workaround
Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4 |
| 54035fc4 | 13-Jan-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Disable non-temporal hint on Cortex-A53/57
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a s
Disable non-temporal hint on Cortex-A53/57
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.
This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.
The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.
Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
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| 820756e9 | 07-Jan-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for ARM Cortex-A35 processor
This patch adds support for ARM Cortex-A35 processor in the CPU
specific framework, as described in the Cortex-A35 TRM (r0p0).
Change-Id: Ief930a0bdf6cd82f6
Add support for ARM Cortex-A35 processor
This patch adds support for ARM Cortex-A35 processor in the CPU
specific framework, as described in the Cortex-A35 TRM (r0p0).
Change-Id: Ief930a0bdf6cd82f6cb1c3b106f591a71c883464
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| d178637d | 14-Dec-2015 |
Juan Castillo <juan.castillo@arm.com> |
Remove dashes from image names: 'BL3-x' --> 'BL3x'
This patch removes the dash character from the image name, to
follow the image terminology in the Trusted Firmware Wiki page:
https://github.c
Remove dashes from image names: 'BL3-x' --> 'BL3x'
This patch removes the dash character from the image name, to
follow the image terminology in the Trusted Firmware Wiki page:
https://github.com/ARM-software/arm-trusted-firmware/wiki
Changes apply to output messages, comments and documentation.
non-ARM platform files have been left unmodified.
Change-Id: Ic2a99be4ed929d52afbeb27ac765ceffce46ed76
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| 1dbe3159 | 18-Nov-2015 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Juno R2: Configure the correct L2 RAM latency values
The default reset values for the L2 Data & Tag RAM latencies on the
Cortex-A72 on Juno R2 are not suitable. This patch modifies
the Juno platform
Juno R2: Configure the correct L2 RAM latency values
The default reset values for the L2 Data & Tag RAM latencies on the
Cortex-A72 on Juno R2 are not suitable. This patch modifies
the Juno platform reset handler to configure the right settings
on Juno R2.
Change-Id: I20953de7ba0619324a389e0b7bbf951b64057db8
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| e0d913c7 | 21-Aug-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Add macros for retention control in Cortex-A53/A57
This patch adds macros suitable for programming the Advanced
SIMD/Floating-point (only Cortex-A53), CPU and L2 dynamic
retention control policy in
Add macros for retention control in Cortex-A53/A57
This patch adds macros suitable for programming the Advanced
SIMD/Floating-point (only Cortex-A53), CPU and L2 dynamic
retention control policy in the CPUECTLR_EL1 and L2ECTLR
registers.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 6b0d97b2 | 29-Jul-2015 |
Jimmy Huang <jimmy.huang@mediatek.com> |
cortex_a53: Add A53 errata #826319, #836870
- Apply a53 errata #826319 to revision <= r0p2
- Apply a53 errata #836870 to revision <= r0p3
- Update docs/cpu-specific-build-macros.md for newly added e
cortex_a53: Add A53 errata #826319, #836870
- Apply a53 errata #826319 to revision <= r0p2
- Apply a53 errata #836870 to revision <= r0p3
- Update docs/cpu-specific-build-macros.md for newly added errata build flags
Change-Id: I44918e36b47dca1fa29695b68700ff9bf888865e
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
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| 3a8c55f6 | 14-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Add "Project Denver" CPU support
Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
fully ARMv8 architecture compatible. Each of the two Denver cores
implements a 7-way supersca
Add "Project Denver" CPU support
Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
fully ARMv8 architecture compatible. Each of the two Denver cores
implements a 7-way superscalar microarchitecture (up to 7 concurrent
micro-ops can be executed per clock), and includes a 128KB 4-way L1
instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
cache, which services both cores.
Denver implements an innovative process called Dynamic Code Optimization,
which optimizes frequently used software routines at runtime into dense,
highly tuned microcode-equivalent routines. These are stored in a
dedicated, 128MB main-memory-based optimization cache. After being read
into the instruction cache, the optimized micro-ops are executed,
re-fetched and executed from the instruction cache as long as needed and
capacity allows.
Effectively, this reduces the need to re-optimize the software routines.
Instead of using hardware to extract the instruction-level parallelism
(ILP) inherent in the code, Denver extracts the ILP once via software
techniques, and then executes those routines repeatedly, thus amortizing
the cost of ILP extraction over the many execution instances.
Denver also features new low latency power-state transitions, in addition
to extensive power-gating and dynamic voltage and clock scaling based on
workloads.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| e2bf57f8 | 01-Apr-2015 |
Dan Handley <dan.handley@arm.com> |
Add header guards to asm macro files
Some assembly files containing macros are included like header files
into other assembly files. This will cause assembler errors if they
are included multiple ti
Add header guards to asm macro files
Some assembly files containing macros are included like header files
into other assembly files. This will cause assembler errors if they
are included multiple times.
Add header guards to assembly macro files to avoid assembler errors.
Change-Id: Ia632e767ed7df7bf507b294982b8d730a6f8fe69
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| 1ba93aeb | 17-Feb-2015 |
Vikram Kanigiri <vikram.kanigiri@arm.com> |
Add support for ARM Cortex-A72 processor
This patch adds support for ARM Cortex-A72 processor in the CPU
specific framework.
Change-Id: I5986855fc1b875aadf3eba8c36e989d8a05e5175 |
| 79a97b2e | 20-Nov-2014 |
Yatharth Kochar <yatharth.kochar@arm.com> |
Call reset handlers upon BL3-1 entry.
This patch adds support to call the reset_handler() function in BL3-1 in the
cold and warm boot paths when another Boot ROM reset_handler() has already run.
Th
Call reset handlers upon BL3-1 entry.
This patch adds support to call the reset_handler() function in BL3-1 in the
cold and warm boot paths when another Boot ROM reset_handler() has already run.
This means the BL1 and BL3-1 versions of the CPU and platform specific reset
handlers may execute different code to each other. This enables a developer to
perform additional actions or undo actions already performed during the first
call of the reset handlers e.g. apply additional errata workarounds.
Typically, the reset handler will be first called from the BL1 Boot ROM. Any
additional functionality can be added to the reset handler when it is called
from BL3-1 resident in RW memory. The constant FIRST_RESET_HANDLER_CALL is used
to identify whether this is the first version of the reset handler code to be
executed or an overridden version of the code.
The Cortex-A57 errata workarounds are applied only if they have not already been
applied.
Fixes ARM-software/tf-issue#275
Change-Id: Id295f106e4fda23d6736debdade2ac7f2a9a9053
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| 01b916bf | 17-Jul-2014 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Juno: Implement initial platform port
This patch adds the initial port of the ARM Trusted Firmware on the Juno
development platform. This port does not support a BL3-2 image or any PSCI APIs
apart f
Juno: Implement initial platform port
This patch adds the initial port of the ARM Trusted Firmware on the Juno
development platform. This port does not support a BL3-2 image or any PSCI APIs
apart from PSCI_VERSION and PSCI_CPU_ON. It enables workarounds for selected
Cortex-A57 (#806969 & #813420) errata and implements the workaround for a Juno
platform errata (Defect id 831273).
Change-Id: Ib3d92df3af53820cfbb2977582ed0d7abf6ef893
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| d9bdaf2d | 14-Aug-2014 |
Soby Mathew <soby.mathew@arm.com> |
Add support for selected Cortex-A57 errata workarounds
This patch adds workarounds for selected errata which affect the Cortex-A57 r0p0
part. Each workaround has a build time flag which should be us
Add support for selected Cortex-A57 errata workarounds
This patch adds workarounds for selected errata which affect the Cortex-A57 r0p0
part. Each workaround has a build time flag which should be used by the platform
port to enable or disable the corresponding workaround. The workarounds are
disabled by default. An assertion is raised if the platform enables a workaround
which does not match the CPU revision at runtime.
Change-Id: I9ae96b01c6ff733d04dc733bd4e67dbf77b29fb0
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| d3f70af6 | 14-Aug-2014 |
Soby Mathew <soby.mathew@arm.com> |
Add CPU specific crash reporting handlers
This patch adds handlers for dumping Cortex-A57 and Cortex-A53 specific register
state to the CPU specific operations framework. The contents of CPUECTLR_EL
Add CPU specific crash reporting handlers
This patch adds handlers for dumping Cortex-A57 and Cortex-A53 specific register
state to the CPU specific operations framework. The contents of CPUECTLR_EL1 are
dumped currently.
Change-Id: I63d3dbfc4ac52fef5e25a8cf6b937c6f0975c8ab
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| add40351 | 14-Aug-2014 |
Soby Mathew <soby.mathew@arm.com> |
Add CPU specific power management operations
This patch adds CPU core and cluster power down sequences to the CPU specific
operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57
Add CPU specific power management operations
This patch adds CPU core and cluster power down sequences to the CPU specific
operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and
generic AEM sequences have been added. The latter is suitable for the
Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is
saved in the per-cpu data so that it can be easily accessed during power down
seqeunces.
An optional platform API has been introduced to allow a platform to disable the
Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak
definition of this function (plat_disable_acp()) does not take any action. It
should be overriden with a strong definition if the ACP is present on a
platform.
Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d
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