1/* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <cortex_a57.h> 34#include <cpu_macros.S> 35#include <plat_macros.S> 36 37 /* --------------------------------------------- 38 * Disable L1 data cache and unified L2 cache 39 * --------------------------------------------- 40 */ 41func cortex_a57_disable_dcache 42 mrs x1, sctlr_el3 43 bic x1, x1, #SCTLR_C_BIT 44 msr sctlr_el3, x1 45 isb 46 ret 47 48 /* --------------------------------------------- 49 * Disable all types of L2 prefetches. 50 * --------------------------------------------- 51 */ 52func cortex_a57_disable_l2_prefetch 53 mrs x0, CPUECTLR_EL1 54 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 55 mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK 56 orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK 57 bic x0, x0, x1 58 msr CPUECTLR_EL1, x0 59 isb 60 dsb sy 61 ret 62 63 /* --------------------------------------------- 64 * Disable intra-cluster coherency 65 * --------------------------------------------- 66 */ 67func cortex_a57_disable_smp 68 mrs x0, CPUECTLR_EL1 69 bic x0, x0, #CPUECTLR_SMP_BIT 70 msr CPUECTLR_EL1, x0 71 ret 72 73 /* --------------------------------------------- 74 * Disable debug interfaces 75 * --------------------------------------------- 76 */ 77func cortex_a57_disable_ext_debug 78 mov x0, #1 79 msr osdlr_el1, x0 80 isb 81 dsb sy 82 ret 83 84func cortex_a57_reset_func 85#if ERRATA_A57_806969 || ERRATA_A57_813420 86 /* --------------------------------------------- 87 * Ensure that the following errata is only 88 * applied on r0p0 parts. 89 * --------------------------------------------- 90 */ 91#if ASM_ASSERTION 92 mrs x0, midr_el1 93 ubfx x1, x0, #MIDR_VAR_SHIFT, #4 94 ubfx x2, x0, #MIDR_REV_SHIFT, #4 95 orr x0, x1, x2 96 cmp x0, #0 97 ASM_ASSERT(eq) 98#endif 99 mov x1, xzr 100#if ERRATA_A57_806969 101 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA 102#endif 103#if ERRATA_A57_813420 104 orr x1, x1, #CPUACTLR_DCC_AS_DCCI 105#endif 106 mrs x0, CPUACTLR_EL1 107 orr x0, x0, x1 108 msr CPUACTLR_EL1, x0 109#endif 110 111 /* --------------------------------------------- 112 * As a bare minimum enable the SMP bit. 113 * --------------------------------------------- 114 */ 115 mrs x0, CPUECTLR_EL1 116 orr x0, x0, #CPUECTLR_SMP_BIT 117 msr CPUECTLR_EL1, x0 118 isb 119 ret 120 121func cortex_a57_core_pwr_dwn 122 mov x18, x30 123 124 /* --------------------------------------------- 125 * Turn off caches. 126 * --------------------------------------------- 127 */ 128 bl cortex_a57_disable_dcache 129 130 /* --------------------------------------------- 131 * Disable the L2 prefetches. 132 * --------------------------------------------- 133 */ 134 bl cortex_a57_disable_l2_prefetch 135 136 /* --------------------------------------------- 137 * Flush L1 cache to PoU. 138 * --------------------------------------------- 139 */ 140 mov x0, #DCCISW 141 bl dcsw_op_louis 142 143 /* --------------------------------------------- 144 * Come out of intra cluster coherency 145 * --------------------------------------------- 146 */ 147 bl cortex_a57_disable_smp 148 149 /* --------------------------------------------- 150 * Force the debug interfaces to be quiescent 151 * --------------------------------------------- 152 */ 153 mov x30, x18 154 b cortex_a57_disable_ext_debug 155 156func cortex_a57_cluster_pwr_dwn 157 mov x18, x30 158 159 /* --------------------------------------------- 160 * Turn off caches. 161 * --------------------------------------------- 162 */ 163 bl cortex_a57_disable_dcache 164 165 /* --------------------------------------------- 166 * Disable the L2 prefetches. 167 * --------------------------------------------- 168 */ 169 bl cortex_a57_disable_l2_prefetch 170 171 /* --------------------------------------------- 172 * Disable the optional ACP. 173 * --------------------------------------------- 174 */ 175 bl plat_disable_acp 176 177 /* --------------------------------------------- 178 * Flush L1 and L2 caches to PoC. 179 * --------------------------------------------- 180 */ 181 mov x0, #DCCISW 182 bl dcsw_op_all 183 184 /* --------------------------------------------- 185 * Come out of intra cluster coherency 186 * --------------------------------------------- 187 */ 188 bl cortex_a57_disable_smp 189 190 /* --------------------------------------------- 191 * Force the debug interfaces to be quiescent 192 * --------------------------------------------- 193 */ 194 mov x30, x18 195 b cortex_a57_disable_ext_debug 196 197 /* --------------------------------------------- 198 * This function provides cortex_a57 specific 199 * register information for crash reporting. 200 * It needs to return with x6 pointing to 201 * a list of register names in ascii and 202 * x8 - x15 having values of registers to be 203 * reported. 204 * --------------------------------------------- 205 */ 206.section .rodata.cortex_a57_regs, "aS" 207cortex_a57_regs: /* The ascii list of register names to be reported */ 208 .asciz "cpuectlr_el1", "" 209 210func cortex_a57_cpu_reg_dump 211 adr x6, cortex_a57_regs 212 mrs x8, CPUECTLR_EL1 213 ret 214 215 216declare_cpu_ops cortex_a57, CORTEX_A57_MIDR 217