1/* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <bl_common.h> 33#include <cortex_a53.h> 34#include <cpu_macros.S> 35#include <plat_macros.S> 36 37 /* --------------------------------------------- 38 * Disable L1 data cache and unified L2 cache 39 * --------------------------------------------- 40 */ 41func cortex_a53_disable_dcache 42 mrs x1, sctlr_el3 43 bic x1, x1, #SCTLR_C_BIT 44 msr sctlr_el3, x1 45 isb 46 ret 47 48 /* --------------------------------------------- 49 * Disable intra-cluster coherency 50 * --------------------------------------------- 51 */ 52func cortex_a53_disable_smp 53 mrs x0, CPUECTLR_EL1 54 bic x0, x0, #CPUECTLR_SMP_BIT 55 msr CPUECTLR_EL1, x0 56 isb 57 dsb sy 58 ret 59 60func cortex_a53_reset_func 61 /* --------------------------------------------- 62 * As a bare minimum enable the SMP bit if it is 63 * not already set. 64 * --------------------------------------------- 65 */ 66 mrs x0, CPUECTLR_EL1 67 tst x0, #CPUECTLR_SMP_BIT 68 b.ne skip_smp_setup 69 orr x0, x0, #CPUECTLR_SMP_BIT 70 msr CPUECTLR_EL1, x0 71 isb 72skip_smp_setup: 73 ret 74 75func cortex_a53_core_pwr_dwn 76 mov x18, x30 77 78 /* --------------------------------------------- 79 * Turn off caches. 80 * --------------------------------------------- 81 */ 82 bl cortex_a53_disable_dcache 83 84 /* --------------------------------------------- 85 * Flush L1 caches. 86 * --------------------------------------------- 87 */ 88 mov x0, #DCCISW 89 bl dcsw_op_level1 90 91 /* --------------------------------------------- 92 * Come out of intra cluster coherency 93 * --------------------------------------------- 94 */ 95 mov x30, x18 96 b cortex_a53_disable_smp 97 98func cortex_a53_cluster_pwr_dwn 99 mov x18, x30 100 101 /* --------------------------------------------- 102 * Turn off caches. 103 * --------------------------------------------- 104 */ 105 bl cortex_a53_disable_dcache 106 107 /* --------------------------------------------- 108 * Flush L1 caches. 109 * --------------------------------------------- 110 */ 111 mov x0, #DCCISW 112 bl dcsw_op_level1 113 114 /* --------------------------------------------- 115 * Disable the optional ACP. 116 * --------------------------------------------- 117 */ 118 bl plat_disable_acp 119 120 /* --------------------------------------------- 121 * Flush L2 caches. 122 * --------------------------------------------- 123 */ 124 mov x0, #DCCISW 125 bl dcsw_op_level2 126 127 /* --------------------------------------------- 128 * Come out of intra cluster coherency 129 * --------------------------------------------- 130 */ 131 mov x30, x18 132 b cortex_a53_disable_smp 133 134 /* --------------------------------------------- 135 * This function provides cortex_a53 specific 136 * register information for crash reporting. 137 * It needs to return with x6 pointing to 138 * a list of register names in ascii and 139 * x8 - x15 having values of registers to be 140 * reported. 141 * --------------------------------------------- 142 */ 143.section .rodata.cortex_a53_regs, "aS" 144cortex_a53_regs: /* The ascii list of register names to be reported */ 145 .asciz "cpuectlr_el1", "" 146 147func cortex_a53_cpu_reg_dump 148 adr x6, cortex_a53_regs 149 mrs x8, CPUECTLR_EL1 150 ret 151 152declare_cpu_ops cortex_a53, CORTEX_A53_MIDR 153