1/* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <bl_common.h> 33#include <cortex_a53.h> 34#include <cpu_macros.S> 35#include <plat_macros.S> 36 37 /* --------------------------------------------- 38 * Disable L1 data cache and unified L2 cache 39 * --------------------------------------------- 40 */ 41func cortex_a53_disable_dcache 42 mrs x1, sctlr_el3 43 bic x1, x1, #SCTLR_C_BIT 44 msr sctlr_el3, x1 45 isb 46 ret 47 48 /* --------------------------------------------- 49 * Disable intra-cluster coherency 50 * --------------------------------------------- 51 */ 52func cortex_a53_disable_smp 53 mrs x0, CPUECTLR_EL1 54 bic x0, x0, #CPUECTLR_SMP_BIT 55 msr CPUECTLR_EL1, x0 56 isb 57 dsb sy 58 ret 59 60func cortex_a53_reset_func 61 /* --------------------------------------------- 62 * As a bare minimum enable the SMP bit if it is 63 * not already set. 64 * Clobbers : x0 65 * --------------------------------------------- 66 */ 67 mrs x0, CPUECTLR_EL1 68 tst x0, #CPUECTLR_SMP_BIT 69 b.ne skip_smp_setup 70 orr x0, x0, #CPUECTLR_SMP_BIT 71 msr CPUECTLR_EL1, x0 72 isb 73skip_smp_setup: 74 ret 75 76func cortex_a53_core_pwr_dwn 77 mov x18, x30 78 79 /* --------------------------------------------- 80 * Turn off caches. 81 * --------------------------------------------- 82 */ 83 bl cortex_a53_disable_dcache 84 85 /* --------------------------------------------- 86 * Flush L1 caches. 87 * --------------------------------------------- 88 */ 89 mov x0, #DCCISW 90 bl dcsw_op_level1 91 92 /* --------------------------------------------- 93 * Come out of intra cluster coherency 94 * --------------------------------------------- 95 */ 96 mov x30, x18 97 b cortex_a53_disable_smp 98 99func cortex_a53_cluster_pwr_dwn 100 mov x18, x30 101 102 /* --------------------------------------------- 103 * Turn off caches. 104 * --------------------------------------------- 105 */ 106 bl cortex_a53_disable_dcache 107 108 /* --------------------------------------------- 109 * Flush L1 caches. 110 * --------------------------------------------- 111 */ 112 mov x0, #DCCISW 113 bl dcsw_op_level1 114 115 /* --------------------------------------------- 116 * Disable the optional ACP. 117 * --------------------------------------------- 118 */ 119 bl plat_disable_acp 120 121 /* --------------------------------------------- 122 * Flush L2 caches. 123 * --------------------------------------------- 124 */ 125 mov x0, #DCCISW 126 bl dcsw_op_level2 127 128 /* --------------------------------------------- 129 * Come out of intra cluster coherency 130 * --------------------------------------------- 131 */ 132 mov x30, x18 133 b cortex_a53_disable_smp 134 135 /* --------------------------------------------- 136 * This function provides cortex_a53 specific 137 * register information for crash reporting. 138 * It needs to return with x6 pointing to 139 * a list of register names in ascii and 140 * x8 - x15 having values of registers to be 141 * reported. 142 * --------------------------------------------- 143 */ 144.section .rodata.cortex_a53_regs, "aS" 145cortex_a53_regs: /* The ascii list of register names to be reported */ 146 .asciz "cpuectlr_el1", "" 147 148func cortex_a53_cpu_reg_dump 149 adr x6, cortex_a53_regs 150 mrs x8, CPUECTLR_EL1 151 ret 152 153declare_cpu_ops cortex_a53, CORTEX_A53_MIDR 154