1/* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <cortex_a57.h> 33#include <cpu_macros.S> 34#include <plat_macros.S> 35 36 /* --------------------------------------------- 37 * Disable L1 data cache and unified L2 cache 38 * --------------------------------------------- 39 */ 40func cortex_a57_disable_dcache 41 mrs x1, sctlr_el3 42 bic x1, x1, #SCTLR_C_BIT 43 msr sctlr_el3, x1 44 isb 45 ret 46 47 /* --------------------------------------------- 48 * Disable all types of L2 prefetches. 49 * --------------------------------------------- 50 */ 51func cortex_a57_disable_l2_prefetch 52 mrs x0, CPUECTLR_EL1 53 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 54 mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK 55 orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK 56 bic x0, x0, x1 57 msr CPUECTLR_EL1, x0 58 isb 59 dsb sy 60 ret 61 62 /* --------------------------------------------- 63 * Disable intra-cluster coherency 64 * --------------------------------------------- 65 */ 66func cortex_a57_disable_smp 67 mrs x0, CPUECTLR_EL1 68 bic x0, x0, #CPUECTLR_SMP_BIT 69 msr CPUECTLR_EL1, x0 70 ret 71 72 /* --------------------------------------------- 73 * Disable debug interfaces 74 * --------------------------------------------- 75 */ 76func cortex_a57_disable_ext_debug 77 mov x0, #1 78 msr osdlr_el1, x0 79 isb 80 dsb sy 81 ret 82 83func cortex_a57_reset_func 84 /* --------------------------------------------- 85 * As a bare minimum enable the SMP bit. 86 * --------------------------------------------- 87 */ 88 mrs x0, CPUECTLR_EL1 89 orr x0, x0, #CPUECTLR_SMP_BIT 90 msr CPUECTLR_EL1, x0 91 isb 92 ret 93 94func cortex_a57_core_pwr_dwn 95 mov x18, x30 96 97 /* --------------------------------------------- 98 * Turn off caches. 99 * --------------------------------------------- 100 */ 101 bl cortex_a57_disable_dcache 102 103 /* --------------------------------------------- 104 * Disable the L2 prefetches. 105 * --------------------------------------------- 106 */ 107 bl cortex_a57_disable_l2_prefetch 108 109 /* --------------------------------------------- 110 * Flush L1 cache to PoU. 111 * --------------------------------------------- 112 */ 113 mov x0, #DCCISW 114 bl dcsw_op_louis 115 116 /* --------------------------------------------- 117 * Come out of intra cluster coherency 118 * --------------------------------------------- 119 */ 120 bl cortex_a57_disable_smp 121 122 /* --------------------------------------------- 123 * Force the debug interfaces to be quiescent 124 * --------------------------------------------- 125 */ 126 mov x30, x18 127 b cortex_a57_disable_ext_debug 128 129func cortex_a57_cluster_pwr_dwn 130 mov x18, x30 131 132 /* --------------------------------------------- 133 * Turn off caches. 134 * --------------------------------------------- 135 */ 136 bl cortex_a57_disable_dcache 137 138 /* --------------------------------------------- 139 * Disable the L2 prefetches. 140 * --------------------------------------------- 141 */ 142 bl cortex_a57_disable_l2_prefetch 143 144 /* --------------------------------------------- 145 * Disable the optional ACP. 146 * --------------------------------------------- 147 */ 148 bl plat_disable_acp 149 150 /* --------------------------------------------- 151 * Flush L1 and L2 caches to PoC. 152 * --------------------------------------------- 153 */ 154 mov x0, #DCCISW 155 bl dcsw_op_all 156 157 /* --------------------------------------------- 158 * Come out of intra cluster coherency 159 * --------------------------------------------- 160 */ 161 bl cortex_a57_disable_smp 162 163 /* --------------------------------------------- 164 * Force the debug interfaces to be quiescent 165 * --------------------------------------------- 166 */ 167 mov x30, x18 168 b cortex_a57_disable_ext_debug 169 170 /* --------------------------------------------- 171 * This function provides cortex_a57 specific 172 * register information for crash reporting. 173 * It needs to return with x6 pointing to 174 * a list of register names in ascii and 175 * x8 - x15 having values of registers to be 176 * reported. 177 * --------------------------------------------- 178 */ 179.section .rodata.cortex_a57_regs, "aS" 180cortex_a57_regs: /* The ascii list of register names to be reported */ 181 .asciz "cpuectlr_el1", "" 182 183func cortex_a57_cpu_reg_dump 184 adr x6, cortex_a57_regs 185 mrs x8, CPUECTLR_EL1 186 ret 187 188 189declare_cpu_ops cortex_a57, CORTEX_A57_MIDR 190